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    Microstructure and method for the production thereof
    61.
    发明申请
    Microstructure and method for the production thereof 失效
    微结构及其制造方法

    公开(公告)号：US20030176007A1

    公开(公告)日：2003-09-18

    申请号：US10296771

    申请日：2002-12-13

    Inventor： Andreas Bertz ,  Thomas Gessner ,  Matthias Kuchler ,  Roman Knofler

    IPC: H01L021/00

    CPC classification number: B81B3/0086 ,  B81B2203/033 ,  B81C2201/016

    Abstract: The invention relates to a microstructure in a preferably electrically conductive substrate (1), more specifically made of doped single crystal silicon, with at least one functional unit (2.1, 2.2) and to a method of fabricating the same. In accordance with the invention, the functional unit (2.1, 2.2) is mechanically and electrically separated from the substrate (1) on all sides by means of isolation gaps (5, 5a) and is connected, on at least one site, to a first structure (4a) of an electrically conductive layer (S) that is electrically isolated from the substrate (1) by way of an isolation layer (3) and that secures the unit into position relative to the substrate (1). For this purpose, the functional unit (2.1, 2.2) is released from the substrate (1) in such a manner that the isolation gaps (5, 5a) are provided on all sides relative to the substrate (1). The electrically conductive layer (S) is applied in such a manner that it is connected through contact fingers (4a) for example to the functional unit (2.1, 2.2) which it secures into position. The method in accordance with the invention permits to substantially facilitate the manufacturing process and to produce a microstructure with but small parasitic capacitances.

    Abstract translation: 本发明涉及在具有至少一个功能单元（2.1,2.2）的优选导电衬底（1）中，更具体地由掺杂单晶硅制成的微观结构及其制造方法。 根据本发明，功能单元（2.1,2.2）通过隔离间隙（5,5a）在所有侧面上与基板​​（1）机械地和电气地分开，并且在至少一个位置上连接到 通过隔离层（3）与衬底（1）电绝缘的导电层（S）的第一结构（4a），并且将单元固定在相对于衬底（1）的位置。 为此，功能单元（2.1,2.2）以这样的方式从基板（1）释放，使得隔离间隙（5,5a）相对于基板（1）设置在所有侧面上。 导电层（S）以这样的方式被施加，使得它通过接触指（4a）例如连接到功能单元（2.1,2.2）上，其被固定到位。 根据本发明的方法允许基本上方便制造过程并产生具有小的寄生电容的微结构。

    Silicon pressure micro-sensing device and the fabrication process
    62.
    发明授权
    Silicon pressure micro-sensing device and the fabrication process 失效
    硅压敏元件及其制造工艺

    公开(公告)号：US06541834B1

    公开(公告)日：2003-04-01

    申请号：US09975125

    申请日：2001-10-09

    Applicant: Jin-shown Shie ,  Ji-cheng Lin ,  Chun-te Lin ,  Chih-tang Peng ,  Shih-han Yu ,  Kuo-ning Chiang

    Inventor： Jin-shown Shie ,  Ji-cheng Lin ,  Chun-te Lin ,  Chih-tang Peng ,  Shih-han Yu ,  Kuo-ning Chiang

    IPC: H01L2982

    CPC classification number: B81C1/00182 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/014 ,  B81C2201/016 ,  G01L9/0054

    Abstract: The invention is a silicon pressure micro-sensing device and the fabrication process thereof. The silicon pressure micro-sensing device includes a pressure chamber, and is constituted of a P-type substrate with a taper chamber and an N-type epitaxial layer thereon. On the N-type epitaxial layer are a plurality of piezo-resistance sensing units which sense deformation caused by pressure. The fabrication pressure of the silicon pressure micro-sensing device includes a step of first making a plurality of holes on the N-type epitaxial layer to reach the P-type substrate beneath. Then, by an anisotropic etching stop technique, in which etchant pass through the holes, a taper chamber is formed in the P-type substrate. Finally, an insulating material is applied to seal the holes, thus attaining the silicon pressure micro-sensing device that is able to sense pressure differences between two ends thereof.

    Abstract translation: 本发明是一种硅压力微型感测装置及其制造方法。 硅压力微型感测装置包括压力室，由具有锥形室的P型衬底和其上的N型外延层构成。 在N型外延层上是感测由压力引起的变形的多个压电感测单元。 硅压力微型感测装置的制造压力包括首先在N型外延层上制造多个孔以到达下面的P型衬底的步骤。 然后，通过各向异性蚀刻停止技术，其中蚀刻剂穿过孔，在P型衬底中形成锥形室。 最后，施加绝缘材料以密封孔，从而获得能够感测其两端之间的压力差的硅压力微检测装置。

    MEMS-CMOS DEVICE THAT MINIMIZES OUTGASSING AND METHODS OF MANUFACTURE
    69.
    发明申请
    MEMS-CMOS DEVICE THAT MINIMIZES OUTGASSING AND METHODS OF MANUFACTURE 有权
    最小化出口的MEMS-CMOS器件和制造方法

    公开(公告)号：US20170073217A1

    公开(公告)日：2017-03-16

    申请号：US15366495

    申请日：2016-12-01

    Applicant: INVENSENSE, INC.

    Inventor： Peter SMEYS ,  Jong Il SHIN ,  Jongwoo SHIN

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/0041 ,  B81B2207/012 ,  B81B2207/094 ,  B81C1/00293 ,  B81C2201/013 ,  B81C2201/0133 ,  B81C2201/016 ,  B81C2203/035 ,  B81C2203/0792

    Abstract: A MEMS device is disclosed. The MEMS device includes a first substrate. At least one structure is formed within the first substrate. The first substrate includes at least one first conductive pad thereon. The MEMS device also includes a second substrate. The second substrate includes a passivation layer. The passivation layer includes a plurality of layers. A top layer of the plurality of layers comprises an outgassing barrier layer. At least one second conductive pad and at least one electrode are coupled to the top layer. At least one first conductive pad is coupled to the at least one second conductive pad.

    Abstract translation: 公开了MEMS器件。 MEMS器件包括第一衬底。 在第一基板内形成至少一个结构。 第一衬底包括至少一个第一导电焊盘。 MEMS器件还包括第二衬底。 第二基板包括钝化层。 钝化层包括多个层。 多个层的顶层包括除气阻挡层。 至少一个第二导电焊盘和至少一个电极耦合到顶层。 至少一个第一导电焊盘耦合到所述至少一个第二导电焊盘。

    MEMS-CMOS device that minimizes outgassing and methods of manufacture
    70.
    发明授权
    MEMS-CMOS device that minimizes outgassing and methods of manufacture 有权
    最小化除气的MEMS-CMOS器件和制造方法

    公开(公告)号：US09540228B2

    公开(公告)日：2017-01-10

    申请号：US14748012

    申请日：2015-06-23

    Applicant: InvenSense, Inc.

    Inventor： Peter Smeys ,  Jong Il Shin ,  Jongwoo Shin

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/0041 ,  B81B2207/012 ,  B81B2207/094 ,  B81C1/00293 ,  B81C2201/013 ,  B81C2201/0133 ,  B81C2201/016 ,  B81C2203/035 ,  B81C2203/0792

    Abstract: A MEMS device is disclosed. The MEMS device includes a first substrate. At least one structure is formed within the first substrate. The first substrate includes at least one first conductive pad thereon. The MEMS device also includes a second substrate. The second substrate includes a passivation layer. The passivation layer includes a plurality of layers. A top layer of the plurality of layers comprises an outgassing barrier layer. At least one second conductive pad and at least one electrode are coupled to the top layer. At least one first conductive pad is coupled to the at least one second conductive pad.

    Abstract translation: 公开了MEMS器件。 MEMS器件包括第一衬底。 在第一基板内形成至少一个结构。 第一衬底包括至少一个第一导电焊盘。 MEMS器件还包括第二衬底。 第二基板包括钝化层。 钝化层包括多个层。 多个层的顶层包括除气阻挡层。 至少一个第二导电焊盘和至少一个电极耦合到顶层。 至少一个第一导电焊盘耦合到所述至少一个第二导电焊盘。

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