公开(公告)号：US07324348B2

公开(公告)日：2008-01-29

申请号：US11171081

申请日：2005-06-28

Applicant: Robin Berg, Jr. ,  Todd Husom ,  Derek Sayres

Inventor： Robin Berg, Jr. ,  Todd Husom ,  Derek Sayres

IPC: H05K5/00

CPC classification number: H04Q1/10 ,  H04Q1/023 ,  H04Q1/03 ,  H04Q1/035 ,  H04Q1/116 ,  H04Q2201/06 ,  H04Q2201/10 ,  H04Q2201/12 ,  H05K1/0216 ,  H05K1/14 ,  H05K1/18 ,  H05K7/1425 ,  H05K7/186 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09354 ,  H05K2201/09663

Abstract: A chassis and associated telecommunication circuit card are disclosed. The chassis has heat dissipation and flame containment features while accommodating a high density of the circuitry cards. Embodiments include an inner housing with a double-layer middle floor dividing the chassis into top and bottom chambers. Each layer has partially aligned slots, and an air gap is provided between the two layers. Embodiments also include a double-layer mesh cover with an air gap existing between the two mesh layers. Projections and grooves are provided on the inner surfaces of the inner housing to receive circuit cards having a guide on one edge and a fin on another. The circuit card includes conductor structures such as multiple board layers with paired and segregated conductors. The circuit card also includes some components positioned to cooperate with the ventilation features of the chassis and includes some components chosen for low-power consumption or reduced flammability.

Abstract translation: 公开了一种底盘和相关通信电路卡。 底盘具有散热和阻燃特征，同时容纳高密度的电路卡。 实施例包括具有双层中间层的内壳，其将底盘分成顶部和底部室。 每个层具有部分对准的槽，并且在两层之间提供气隙。 实施例还包括在两个网格层之间具有气隙的双层网状覆盖物。 在内壳体的内表面上设置突起和凹槽，以接收在一个边缘上具有引导件的电路卡和另一边缘上的翅片。 电路卡包括导体结构，例如具有配对和分离的导体的多个板层。 电路卡还包括定位成与底盘的通风特征配合的一些组件，并且包括一些选择用于低功耗或降低可燃性的组件。

公开(公告)号：US20070289771A1

公开(公告)日：2007-12-20

申请号：US11755045

申请日：2007-05-30

Applicant: HIDEKI OSAKA ,  YUTAKA UEMATSU ,  EIICHI SUZUKI

Inventor： HIDEKI OSAKA ,  YUTAKA UEMATSU ,  EIICHI SUZUKI

IPC: H05K1/00

CPC classification number: H05K1/0236 ,  H01L23/66 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/09972 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention realizes high density mounting along with achieving power source sharing by a digital semiconductor element and an analog semiconductor element in a semiconductor device. An power layer for analog is connected to one end of an EBG layer, a power layer for digital is connected to the other end of the EBG layer, ground terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for analog and the EBG layer from each other is disposed between the power layer for analog and the EBG layer. Thereby, high density mounting is achieved along with reducing interference of power source to an analog chip.

Abstract translation: 本发明通过数字半导体元件和半导体器件中的模拟半导体元件实现电源共享，实现了高密度安装。 用于模拟的功率层连接到EBG层的一端，用于数字的功率层连接到EBG层的另一端，各个元件的接地端子连接到公共接地层，接地层用于 将模拟功率层和EBG层彼此分离设置在用于模拟的功率层和EBG层之间。 因此，实现了高密度安装，同时降低了电源对模拟芯片的干扰。

公开(公告)号：US07304858B2

公开(公告)日：2007-12-04

申请号：US11023489

申请日：2004-12-29

Applicant: Akiyoshi Saitou

Inventor： Akiyoshi Saitou

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0233 ,  H05K1/0215 ,  H05K1/0224 ,  H05K1/18 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10189 ,  H05K2201/10409

Abstract: A printed circuit board has separate first, second and third sections arranged in a predetermined direction. A connector is mounted at the first section. A noise cut filter is mounted at the second section and connected to the connector. An electronic circuit component is mounted at the third section and connected to the noise cut filter. An electrically conductive power source layer is formed within the printed circuit board at a position outside a peripheral section adjacent the second section. The noise cut filter is allowed to operate without receiving any influence of noise from the power source layer. Noise is sufficiently removed at the noise cut filter. Noise is suppressed to the utmost in electric signals in the connector. Radiation of noise is reliably reduced at the connector. Electromagnetic interference can be suppressed.

Abstract translation: 印刷电路板具有沿预定方向布置的单独的第一，第二和第三部分。 连接器安装在第一部分。 噪声截止滤波器安装在第二部分并连接到连接器。 电子电路部件安装在第三部分并连接到噪声截止滤波器。 在印刷电路板的与第二部分相邻的周边部分外的位置处形成导电电源层。 允许噪声抑制滤波器工作，而不会受到来自电源层的噪声的任何影响。 噪声在噪音截止滤波器上被充分去除。 连接器中的电信号最大限度地抑制噪声。 连接器可靠地降低噪声辐射。 可以抑制电磁干扰。

公开(公告)号：US07282647B2

公开(公告)日：2007-10-16

申请号：US10329188

申请日：2002-12-23

Applicant: Weston Roth ,  Jayne L. Mershon ,  Xang Moua ,  Jason A. Mix

Inventor： Weston Roth ,  Jayne L. Mershon ,  Xang Moua ,  Jason A. Mix

IPC: H05K1/03

CPC classification number: H05K1/0234 ,  H05K1/0225 ,  H05K1/0227 ,  H05K1/023 ,  H05K1/167 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.

Abstract translation: 本发明涉及一种用于改善电路板上的平面不连续性的耦合的装置和方法。 电路板包括形成在电压参考平面上的不连续性，例如分裂，槽或切口。 导电层覆盖不连续点。 导电层具有连接到下面的参考平面的第一部分和跨越不连续部分的第二部分。 第一部分使用插槽或通孔连接到参考平面。 并且导电层具有在参考平面上延伸但保持与其断开的第三部分。 导电层可以是石墨或炭黑。

公开(公告)号：US07276668B2

公开(公告)日：2007-10-02

申请号：US10964619

申请日：2004-10-15

Applicant: Sheng-Yuan Lee ,  Ya-Chi Liao

Inventor： Sheng-Yuan Lee ,  Ya-Chi Liao

IPC: H05K1/03

CPC classification number: H05K1/025 ,  H05K1/0224 ,  H05K1/0231 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A circuit board with mounting pads is described for improving the frequency response of routing traces. The present invention is used to etch an etching hole on ground layer corresponding to the surface-mounted devices (SMD) on a routing layer and therefore the parasitic effect from the stray capacitor is reduced, resulting in eliminating the parasitic effect in high-frequency and raising the quality of the PCB as well.

Abstract translation: 描述了具有安装焊盘的电路板，用于改善路由迹线的频率响应。 本发明用于蚀刻对应于路由层上的表面安装器件（SMD）的接地层上的蚀刻孔，因此来自杂散电容器的寄生效应降低，从而消除了高频下的寄生效应， 提高PCB的质量。

公开(公告)号：US20070222052A1

公开(公告)日：2007-09-27

申请号：US11690482

申请日：2007-03-23

Applicant: Masanao Kabumoto

Inventor： Masanao Kabumoto

IPC: H01L23/02

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01P3/08 ,  H05K1/0224 ,  H05K1/0245 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/0969 ,  H01L2924/00

Abstract: A wiring structure includes a general signal line, a differential signal line having a pair of signal wiring lines and a reference potential layer. The signal wiring lines respectively transmit differential signals of which waveforms are inverted from each other. The reference potential layer is arranged to have a distance from the general signal line and the differential signal line, and has a non-formed portion in a region to be electromagnetically coupled to the differential signal line.

Abstract translation: 布线结构包括通用信号线，具有一对信号布线和参考电位层的差分信号线。 信号线分别发送波形彼此反转的差分信号。 参考电位层被布置成与一般信号线和差分信号线具有一定距离，并且在要被电磁耦合到差分信号线的区域中具有非形成部分。

公开(公告)号：US20070205780A1

公开(公告)日：2007-09-06

申请号：US11308094

申请日：2006-03-06

Applicant: Benjamin Eldridge

Inventor： Benjamin Eldridge

IPC: G01R31/02

CPC classification number: G01R1/07378 ,  G01R31/2889 ,  H05K1/0216 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09672

Abstract: Systems and methods for providing a stack with a guard plane embedded in the stack are disclosed. An electrical apparatus can be made by forming a stack comprising an electrically conductive signal structure, an electrical guard structure, and an electrically insulating structure disposed between the signal structure and the guard structure. The signal structure, insulating structure, and guard structure can be aligned one with another in the stack.

Abstract translation: 公开了一种用于提供具有嵌入堆叠中的保护平面的堆叠的系统和方法。 可以通过形成包括导电信号结构，电保护结构和布置在信号结构和保护结构之间的电绝缘结构的堆叠来制造电气设备。 信号结构，绝缘结构和防护结构可以在堆叠中彼此对准。

公开(公告)号：US20070194433A1

公开(公告)日：2007-08-23

申请号：US10592948

申请日：2004-03-19

Applicant: Motoo Suwa ,  Yoshinori Miyaki ,  Toru Hayashi ,  Ryoichi Sano ,  Shigezumi Matsui ,  Takanobu Naruse ,  Takashi Sato ,  Hisashi Shiota

Inventor： Motoo Suwa ,  Yoshinori Miyaki ,  Toru Hayashi ,  Ryoichi Sano ,  Shigezumi Matsui ,  Takanobu Naruse ,  Takashi Sato ,  Hisashi Shiota

IPC: H01L23/12

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic circuit includes a first semiconductor device (4) and a second semiconductor device (3) on a mounting substrate. The mounting substrate includes a plurality of mounting substrate lines (201 to 204) which are connected in common with external terminals of a plurality of bits of the first semiconductor device and external terminals of a plurality of bits of the second semiconductor device for every bit. The mounting substrate lines have lengths thereof from the external terminals of the first semiconductor device to the external terminals of the second semiconductor device made unequal for respective bits. Assembling lines (361 to 364) which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. Here, the unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines. According to such a constitution, it is unnecessary to set lengths between the external terminals of the second semiconductor device and the connecting electrodes of the semiconductor chip equal.

Abstract translation: 电子电路包括在安装基板上的第一半导体器件（4）和第二半导体器件（3）。 安装基板包括与第一半导体器件的多个位的外部端子和第二半导体器件的多个位的外部端子共同连接的多个安装基板线（201〜204）。 安装基板线具有从第一半导体器件的外部端子到对于各个位不相等的第二半导体器件的外部端子的长度。 从第二半导体器件的外部端子到达半导体芯片的连接电极的组装线（361至364）使其长度对于各个位不相等。 这里，安装基板线的不等长度具有抵消装配线的不等长度的关系。 根据这种结构，不需要在第二半导体器件的外部端子和半导体芯片的连接电极之间设置长度相等。

公开(公告)号：US07259968B2

公开(公告)日：2007-08-21

申请号：US10437619

申请日：2003-05-14

Applicant: Mitchel E. Wright

Inventor： Mitchel E. Wright

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0253 ,  H05K1/0224 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/09972

Abstract: A multi-layer circuit board includes a first layer having at least first and second conductive traces of different widths and the same impedance. One of a first power plane and first ground plane has a void region such that the first conductive trace is spaced apart from the first power plane by a first thickness, and the second conductive trace is spaced apart from the first ground plane by a second, different thickness.

Abstract translation: 多层电路板包括具有不同宽度和相同阻抗的至少第一和第二导电迹线的第一层。 第一电力平面和第一接地平面中的一个具有空隙区域，使得第一导电迹线与第一电力平面间隔第一厚度，并且第二导电迹线与第一接地平面间隔开第二导电迹线， 不同厚度。

公开(公告)号：US20070134953A1

公开(公告)日：2007-06-14

申请号：US11298998

申请日：2005-12-09

Applicant: Francis Morana ,  Dennis Dupler ,  Charles Adams

Inventor： Francis Morana ,  Dennis Dupler ,  Charles Adams

IPC: H01R12/00

CPC classification number: H01R13/6477 ,  H01R13/6658 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K1/117 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/10189 ,  Y10S439/941

Abstract: An electrical connector comprises a housing holding a circuit board. The circuit board has a top surface which includes a first region and a second region. Circuit traces are formed on the top surface and extend in the first and second regions. A first ground plane is disposed at a first depth in the circuit board below the circuit traces in the first region. The first depth is selected to provide a specific characteristic impedance of the circuit traces in the first region. A second ground plane is disposed at a second depth in the circuit board below the circuit traces in the second region. The second depth is selected to provide a specific characteristic impedance of the circuit traces in the second region.

Abstract translation: 电连接器包括容纳电路板的壳体。 电路板具有包括第一区域和第二区域的顶表面。 电路迹线形成在顶表面上并且在第一和第二区域中延伸。 第一接地平面设置在第一区域中的电路迹线下方的电路板中的第一深度处。 选择第一深度以在第一区域中提供电路迹线的特定阻抗。 第二接地平面设置在第二区域中的电路迹线下方的电路板中的第二深度处。 选择第二深度以在第二区域中提供电路迹线的特定阻抗。