公开(公告)号：US07977034B1

公开(公告)日：2011-07-12

申请号：US12657394

申请日：2010-01-20

Applicant: John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, Jr. ,  Peter A. Moschak

Inventor： John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, Jr. ,  Peter A. Moschak

IPC: H05K3/02 ,  H05K3/06

CPC classification number: H05K3/4641 ,  H05K3/064 ,  H05K3/4069 ,  H05K3/427 ,  H05K3/44 ,  H05K3/445 ,  H05K3/462 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0143 ,  H05K2203/068 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Apparatus and method for making circuitized substrates using a continuous roll format in which a layer of conductor is fed into the apparatus, layers of photo-imageable dielectric are applied to opposite sides of the conductor layer, thru-holes are formed through the composite, and then metal layers are added over the dielectric and then patterns (e.g., circuit) are formed therein. Several operations are performed in addition to these to form the final end product, a circuitized substrate (e.g., printed circuit board), all while the conductor layer of the product is retained in a solid format, up to the final separation from the continuous layer.

Abstract translation: 使用连续辊式制造电路化基板的装置和方法，其中导体层被馈送到装置中，可光成像电介质层被施加到导体层的相对侧，穿过复合材料形成通孔， 然后在电介质上添加金属层，然后在其中形成图案（例如电路）。 除了这些之外，还进行了几个操作以形成最终终端产品，电路化基板（例如，印刷电路板），同时产品的导体层保持为固体形式，直到与连续层的最终分离 。

公开(公告)号：US07898069B2

公开(公告)日：2011-03-01

申请号：US12365606

申请日：2009-02-04

Applicant: Rajiv C Dunne

Inventor： Rajiv C Dunne

IPC: H01L23/02

CPC classification number: H01L23/5389 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H05K1/186 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/10515 ,  H05K2203/063 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor system having a substrate (101) including a rigid insulating interposer (110) with a high modulus and a top (140) and a bottom (150) low-modulus tape with flip-attached semiconductor chips (120, 130). The assembled chips, with the passive surfaces facing each other, are located in an opening (114) of the interposer, which has a thickness (111) equal to or smaller than the sum of the assembled two chips. Adhesive material (160) holds the tapes parallel to the interposer and the chip surfaces together. Solder balls (180) and discrete components (170) may be attached to the outside surfaces of the tapes.

Abstract translation: 一种具有衬底（101）的半导体系统，包括具有高模量的刚性绝缘插入件（110）和具有翻转连接的半导体芯片（120,130）的顶部（140）和底部（150）低模量带。 具有被动表面彼此相对的组装芯片位于插入件的开口（114）中，其具有等于或小于组装的两个芯片的总和的厚度（111）。 粘合材料（160）将带平行于插入件并将芯片表面保持在一起。 焊球（180）和分立部件（170）可以附接到带的外表面。

公开(公告)号：US20110024164A1

公开(公告)日：2011-02-03

申请号：US12887197

申请日：2010-09-21

Applicant: Motoo ASAI ,  Dongdong WANG ,  Takahiro MORI

Inventor： Motoo ASAI ,  Dongdong WANG ,  Takahiro MORI

IPC: H05K1/03

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a core structure comprising resin layers and conductor circuits sandwiched by the resin layers, the core structure having a first surface and a second surface on an opposite side of the first surface, a first conductor layer including conductor circuits formed on the first surface of the core structure, and a second conductor layer including conductor circuits formed on the second surface of the core structure. The core structure includes a first via hole and a second via hole, and the first via hole and the second via hole include a metal filling up to the respective top of openings formed in the resin layers, respectively, sandwich one or more conductor circuits in the core structure and are positioned vertically to form a through hole electrically connecting respective ones of the conductor circuits of the first and the second conductor layers.

Abstract translation: 一种多层印刷电路板，包括由树脂层和由树脂层夹持的导体电路的芯结构，芯结构具有在第一表面的相对侧上的第一表面和第二表面，第一导体层包括导体电路 形成在芯结构的第一表面上，以及第二导体层，包括形成在芯结构的第二表面上的导体电路。 芯结构包括第一通孔和第二通孔，并且第一通孔和第二通孔分别包括填充到树脂层中形成的开口的相应顶部的金属，将一个或多个导体电路夹在 芯结构并且垂直定位以形成电连接第一和第二导体层的各个导体电路的通孔。

公开(公告)号：US20110006861A1

公开(公告)日：2011-01-13

申请号：US12854617

申请日：2010-08-11

Applicant: George E. White ,  Madhavan Swaminathan ,  Venkatesh Sundaram ,  Sidharth Dalmia

Inventor： George E. White ,  Madhavan Swaminathan ,  Venkatesh Sundaram ,  Sidharth Dalmia

IPC: H01P1/20

CPC classification number: H05K1/16 ,  H01L23/552 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P1/203 ,  H01P1/20381 ,  H01P1/2135 ,  H01P5/10 ,  H03H7/0115 ,  H03H7/075 ,  H03H7/09 ,  H03H7/1708 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/1775 ,  H03H7/38 ,  H03H7/42 ,  H03H7/463 ,  H03H2001/0085 ,  H05K1/024 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4644 ,  H05K3/4673 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/09536 ,  H01L2924/00

Abstract: The present invention provides all organic fully-packaged miniature bandpass filters, baluns, diplexers, multiplexers, couplers and a combination of the above manufactured using liquid crystalline polymer (LCP) and other multilayer polymer based substrates. These devices are manufactured using one or more LCP layers having integrated passive components formed thereon to provide the density and performance necessary for multi-band wireless devices. In the designs involving multiple LCP layers, the LCP layers are separated by prepeg layers. In accordance with an aspect of the present invention, coplanar waveguide, hybrid stripline/coplanar waveguide and/or microstrip topologies are utilized to form the integrated passive components, and the devices can be mass produced on large area panels at least 18 inches by 12 inches with line widths smaller than 10 um.

Abstract translation: 本发明提供了使用液晶聚合物（LCP）和其它多层聚合物基底板制造的所有有机全封装微型带通滤光器，平衡 - 不平衡转换器，双工器，多路复用器，耦合器和上述组合。 这些设备使用一个或多个LCP层制造，其中形成有集成的无源元件，以提供多频带无线设备所需的密度和性能。 在涉及多个LCP层的设计中，LCP层被预制层隔开。 根据本发明的一个方面，共面波导，混合带状线/共面波导和/或微带线拓扑被用于形成集成的无源部件，并且可以在大面积的面板上批量生产至少18英寸×12英寸 线宽小于10um。

公开(公告)号：US20100321914A1

公开(公告)日：2010-12-23

申请号：US12869841

申请日：2010-08-27

Applicant: Yasushi INAGAKI ,  Katsuyuki Sano

Inventor： Yasushi INAGAKI ,  Katsuyuki Sano

IPC: H05K1/18

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/056 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/09736 ,  H05K2201/098 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multilayer printed wiring board in which interlayer insulation layer and conductive layer are formed on a multilayer core substrate composed of three or more layers, having through holes for connecting the front surface with the rear surface and conductive layers on the front and rear surfaces and conductive layer in the inner layer to achieve electric connection through via holes, the through holes being composed of power source through holes, grounding through holes and signal through holes connected electrically to a power source circuit or a grounding circuit or a signal circuit of an IC chip, when the power source through holes pass through the grounding conductive layer of the inner layer in the core substrate, of the power source through holes, at least a power source through hole just below the IC having no conductive circuit extending from the power source through hole in the grounding conductive layer.

Abstract translation: 一种多层印刷电路板，其中层间绝缘层和导电层形成在由三层或更多层组成的多层芯基板上，具有用于将前表面与后表面连接的通孔和前表面和后表面上的导电层，并具有导电性 层，通过通孔进行电连接，通孔由电源通孔，接地通孔和与电源电路或接地电路或IC芯片的信号电路电连接的信号通孔组成， 当电源通孔穿过核心基板中的内层的接地导电层时，通过电源通孔，至少在IC下面至少有一个电源通孔，IC上没有从电源延伸的导电电路， 接地导电层中的孔。

公开(公告)号：US20100319973A1

公开(公告)日：2010-12-23

申请号：US12851803

申请日：2010-08-06

Applicant: Chih-Peng Fan

Inventor： Chih-Peng Fan

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a first core circuit board, at least one embedded capacitor, a second core circuit board and a dielectric layer. The first core circuit board has at least one metal layer, and the first core circuit board has at least one first conductive through hole connected to the metal layer. At least one embedded capacitor is embedded in the first core circuit board and connected to the metal layer. The second core circuit board has at least one wiring layer, and the second core circuit board has at least one second conductive through hole connected to the wiring layer. The dielectric layer is laminated between the first core circuit board and the second core circuit board.

Abstract translation: 提供具有嵌入式电容器的封装基板。 封装衬底包括第一核心电路板，至少一个嵌入式电容器，第二核心电路板和电介质层。 第一核心电路板具有至少一个金属层，并且第一核心电路板具有连接到金属层的至少一个第一导电通孔。 至少一个嵌入式电容器被嵌入在第一核心电路板中并连接到金属层。 第二核心电路板具有至少一个布线层，并且第二核心电路板具有连接到布线层的至少一个第二导电通孔。 电介质层层压在第一芯电路板和第二芯电路板之间。

公开(公告)号：US07839650B2

公开(公告)日：2010-11-23

申请号：US11977780

申请日：2007-10-25

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H05K1/18

CPC classification number: H05K1/162 ,  H05K3/107 ,  H05K3/108 ,  H05K3/426 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09536 ,  H05K2201/09672 ,  Y10T29/49146

Abstract: The present invention provides a circuit board structure having an embedded capacitor and a method for fabricating the same. The circuit board structure includes a core layer board with at least one surface having non-penetrating first and second grooves, a circuit layer and a first electrode plate formed in the first and second grooves of the core layer board respectively and being flush with the core layer board; a high dielectric material layer formed on the core layer board, the circuit layer and the first electrode plate; a second electrode plate formed on the high dielectric material layer and corresponding to the first electrode plate, thereby forming a capacitor by the first and second electrode plates and the high dielectric material layer. The high dielectric material layer is formed on a plane surface so as to eliminate poor filling and improve reliability.

Abstract translation: 本发明提供一种具有嵌入式电容器的电路板结构及其制造方法。 电路板结构包括具有至少一个具有非穿透性第一和第二槽的表面的芯层板，分别形成在芯层板的第一和第二槽中的电路层和第一电极板，并且与芯体齐平 层板; 形成在所述芯层基板，所述电路层和所述第一电极板上的高介电材料层; 形成在高电介质材料层上并对应于第一电极板的第二电极板，从而通过第一和第二电极板和高电介质材料层形成电容器。 高介电材料层形成在平面上，以消除填充不良，提高可靠性。

公开(公告)号：US20100288544A1

公开(公告)日：2010-11-18

申请号：US12842431

申请日：2010-07-23

Applicant: Takashi Kariya

Inventor： Takashi Kariya

IPC: H05K1/00 ,  H05K3/10

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/113 ,  H05K1/115 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10674 ,  Y10T29/49139

Abstract: A multilayer printed wiring board including a core substrate, a built-up wiring layer having a first surface in contact with the substrate and a second surface, the second surface including a mounting area for mounting a semiconductor device, the built-up layer including circuits and insulating layers, first through-hole conductors formed in a first portion of the substrate which corresponds to the mounting area, second through-hole conductors formed in a second portion of the substrate which corresponds to an area of the second surface other than the mounting area, third through-hole conductors formed in a processor core area of the first portion of the substrate which corresponds to a processor core section of the device, and pads provided on the second surface. The first conductors have a pitch smaller than a pitch of the second conductors, and the third conductors have a pitch smaller than the pitch of the first conductors.

Abstract translation: 一种多层印刷电路板，包括芯基板，具有与基板接触的第一表面的积层布线层和第二表面，所述第二表面包括用于安装半导体器件的安装区域，所述堆叠层包括电路 和绝缘层，形成在所述基板的与所述安装区域对应的第一部分中的第一通孔导体，形成在所述基板的第二部分中的第二通孔导体，所述第二通孔导体对应于所述第二表面的除了所述安装 形成在基板的第一部分的处理器核心区域中的区域，第三通孔导体，其对应于设备的处理器核心部分，以及焊盘，设置在第二表面上。 第一导体的间距小于第二导体的间距，第三导体的间距小于第一导体的间距。

公开(公告)号：US07830018B2

公开(公告)日：2010-11-09

申请号：US11863579

申请日：2007-09-28

Applicant: Teck Kheng Lee

Inventor： Teck Kheng Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K13/00 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09854 ,  H01L2924/00

Abstract: Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.

Abstract translation: 包括这种通孔和互连的分隔的过孔，互连和衬底在本文中公开。 在一个实施例中，衬底具有形成在非导电层的一部分中的非导电层和分隔通孔。 非导电层包括在顶侧和底侧之间延伸的顶侧，底侧和通孔，并且包括具有第一部分和第二部分的侧壁。 分隔通孔包括在侧壁的第一部分上的通孔内的第一金属互连和在侧壁的第二部分上的通孔内的第二金属互连，并与第一金属互连电隔离。 在另一个实施例中，第一金属互连通过通孔内的间隙与第二金属互连分开。

公开(公告)号：US07827682B2

公开(公告)日：2010-11-09

申请号：US11110920

申请日：2005-04-21

Applicant: John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, Jr. ,  Peter A. Moschak

Inventor： John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, Jr. ,  Peter A. Moschak

IPC: H05K3/10 ,  G03F7/16

CPC classification number: H05K3/4641 ,  H05K3/064 ,  H05K3/4069 ,  H05K3/427 ,  H05K3/44 ,  H05K3/445 ,  H05K3/462 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0143 ,  H05K2203/068 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Apparatus and method for making circuitized substrates using a continuous roll format in which a layer of conductor is fed into the apparatus, layers of photo-imageable dielectric are applied to opposite sides of the conductor layer, thru-holes are formed through the composite, and then metal layers are added over the dielectric and then patterns (e.g., circuit) are formed therein. Several operations are performed in addition to these to form the final end product, a circuitized substrate (e.g., printed circuit board), all while the conductor layer of the product is retained in a solid format, up to the final separation from the continuous layer.

Abstract translation: 使用连续辊式制造电路化基板的装置和方法，其中导体层被馈送到装置中，可光成像电介质层被施加到导体层的相对侧，穿过复合材料形成通孔， 然后在电介质上添加金属层，然后在其中形成图案（例如电路）。 除了这些之外，还进行了几个操作以形成最终终端产品，电路化基板（例如，印刷电路板），同时产品的导体层保持为固体形式，直到与连续层的最终分离 。