公开(公告)号：US08242010B2

公开(公告)日：2012-08-14

申请号：US12787503

申请日：2010-05-26

Applicant: Stephen Leslie Buchwalter ,  Bruce K. Furman ,  Peter A. Gruber ,  Jae-Woong Nah ,  Da-Yuan Shih

Inventor： Stephen Leslie Buchwalter ,  Bruce K. Furman ,  Peter A. Gruber ,  Jae-Woong Nah ,  Da-Yuan Shih

IPC: H01L21/44

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/28 ,  H01L24/31 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/11822 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10242 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49165 ,  H01L2224/45111 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.

Abstract translation: 电互连形成方法。 电互连包括包括第一导电焊盘的第一衬底，包括第二导电焊盘的第二衬底以及将第一导电焊盘电连接和机械地连接到第二导电焊盘的互连结构。 互连结构包括非焊料金属芯结构，第一焊料结构和第二焊料结构。 第一焊料结构将非焊料金属芯结构的第一部分电连接并机械地连接到第一导电焊盘。 第二焊料结构将非焊料金属芯结构的第二部分电连接并机械连接到第二导电焊盘。

公开(公告)号：US20120111607A1

公开(公告)日：2012-05-10

申请号：US13354438

申请日：2012-01-20

Applicant: Shuhichi OKABE ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi OKABE ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/02

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.

Abstract translation: 一种电路板，包括：具有沟槽的绝缘体; 形成为埋入沟槽的一部分的第一电路图案; 以及形成在其中形成有沟槽的绝缘体的表面上的第二电路图案。

公开(公告)号：US20120084976A1

公开(公告)日：2012-04-12

申请号：US12951245

申请日：2010-11-22

Applicant: Chien-Nan Yu ,  Chung-Feng Tsao ,  Hang-Kau Khor ,  Wen-Chi Shih ,  Ying-Chieh Chen ,  Yu-Hsiao Li

Inventor： Chien-Nan Yu ,  Chung-Feng Tsao ,  Hang-Kau Khor ,  Wen-Chi Shih ,  Ying-Chieh Chen ,  Yu-Hsiao Li

IPC: H05K3/30

CPC classification number: H05K3/305 ,  H01L27/14618 ,  H01L2224/16245 ,  H04N5/2253 ,  H04N5/2257 ,  H05K3/4015 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/09072 ,  H05K2201/10151 ,  H05K2203/0278 ,  H05K2203/1147 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49151

Abstract: The present invention discloses a method for assembling a camera module. The method includes putting plural conductive bumps on a conductive contact of a substrate such that a large conductive bump is formed, and pressing the substrate and an image chip together such that the conductive contact contacts with a pad formed on the image chip through the large conductive bump to combine the conductive contact and the pad. Since there is no contact between the substrate and the image chip but the large conductive bump, the method decreases the probability for fracture between the substrate and the image chip and improves the quality of the camera module.

Abstract translation: 本发明公开了一种组装相机模块的方法。 该方法包括将多个导电凸块放置在基板的导电接触件上，使得形成大的导电凸块，并将基板和图像芯片压在一起，使得导电触点与形成在图像芯片上的焊盘通过大导电 撞击组合导电触点和焊盘。 由于基板和图像芯片之间没有接触，而是大的导电凸块，所以该方法降低了基板和图像芯片之间的断裂概率，并提高了相机模块的质量。

公开(公告)号：US08033016B2

公开(公告)日：2011-10-11

申请号：US11883801

申请日：2006-04-14

Applicant: Kunio Hibino ,  Yoshihiro Tomura ,  Yoshihiko Yagi ,  Kazuhiro Nishikawa

Inventor： Kunio Hibino ,  Yoshihiro Tomura ,  Yoshihiko Yagi ,  Kazuhiro Nishikawa

IPC: H01K3/10

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/11901 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/207 ,  H05K3/245 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2203/0113 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A protruding electrodes is formed on a lead electrode of an electronic component, and the protruding electrodes comprises a first conductor formed on the lead electrode of the electronic component, and a second conductor overlaid on the first conductor by using a transfer mold having a concavity. By virtue of this structure, protruding electrodes of any configuration can be formed in fine pitches.

Abstract translation: 在电子部件的引线电极上形成突起电极，突出电极包括形成在电子部件的引线电极上的第一导体和通过使用具有凹度的转移模具覆盖在第一导体上的第二导体。 通过这种结构，可以以细间距形成任何构造的突出电极。

公开(公告)号：US08018047B2

公开(公告)日：2011-09-13

申请号：US12624622

申请日：2009-11-24

Applicant: Reinhold Bayerer ,  Thomas Hunger

Inventor： Reinhold Bayerer ,  Thomas Hunger

IPC: H01L23/053 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/3735 ,  H01L23/3731 ,  H01L23/3736 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/072 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48699 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/0256 ,  H05K1/0306 ,  H05K1/053 ,  H05K3/4046 ,  H05K3/4061 ,  H05K3/44 ,  H05K3/462 ,  H05K3/4629 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09145 ,  H05K2201/09554 ,  H05K2201/09845 ,  H05K2201/10234 ,  H01L2224/8382 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/83205 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor module includes a multilayer substrate. The multilayer substrate includes a first metal layer and a first ceramic layer over the first metal layer. An edge of the first ceramic layer extends beyond an edge of the first metal layer. The multilayer substrate includes a second metal layer over the first ceramic layer and a second ceramic layer over the second metal layer. An edge of the second ceramic layer extends beyond an edge of the second metal layer. The multilayer substrate includes a third metal layer over the second ceramic layer.

Abstract translation: 半导体模块包括多层基板。 多层基板包括第一金属层和第一金属层上的第一陶瓷层。 第一陶瓷层的边缘延伸超过第一金属层的边缘。 多层基板包括在第一陶瓷层之上的第二金属层和在第二金属层上的第二陶瓷层。 第二陶瓷层的边缘延伸超过第二金属层的边缘。 多层基板包括在第二陶瓷层上的第三金属层。

公开(公告)号：US20110169022A1

公开(公告)日：2011-07-14

申请号：US13063983

申请日：2009-06-02

Applicant: Motoji Shiota ,  Gen Nagaoka ,  Ichiro Umekawa ,  Yasuhiro Hida ,  Yukio Shimizu

Inventor： Motoji Shiota ,  Gen Nagaoka ,  Ichiro Umekawa ,  Yasuhiro Hida ,  Yukio Shimizu

IPC: H01L23/488 ,  H01L33/62 ,  H01L21/60

CPC classification number: H05K3/323 ,  G02F1/13452 ,  H01L2224/73204 ,  H01L2924/07811 ,  H05K1/0231 ,  H05K3/284 ,  H05K3/361 ,  H05K2201/0379 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: A liquid crystal display device (100) includes a glass substrate (110) having an LSI chip (130) and an FPC board (140) mounted thereon. A component ACF (150a) made of a single sheet is used to further mount discrete electronic components such as stabilizing capacitors (150) on the glass substrate (110). The component ACF (150a) has a size that covers not only a region where the discrete electronic components are to be mounted, but also the top surfaces of the LSI chip (130) and the FPC board (140) which are mounted first. By thus using the large component ACF (150a), a positional constraint upon adhering the component ACF (150a) to the glass substrate (110) is eliminated, reducing the area of a region where the discrete electronic components are mounted. By this, a board module miniaturized by reducing the area of a region where discrete electronic components are mounted is provided.

Abstract translation: 液晶显示装置（100）具有安装有LSI芯片（130）的玻璃基板（110）和FPC基板（140）。 使用由单片制成的部件ACF（150a），以进一步将诸如稳定电容器（150）的分立电子部件安装在玻璃基板（110）上。 部件ACF（150a）的尺寸不仅覆盖要安装分立电子部件的区域，而且覆盖首先安装的LSI芯片（130）和FPC基板（140）的顶表面。 通过这样使用大分量ACF（150a），消除了将部件ACF（150a）粘附到玻璃基板（110）上的位置约束，减小了安装分立电子部件的区域的面积。 由此，提供了通过减小​​安装有分立电子部件的区域的面积而小型化的板模块。

公开(公告)号：US07879445B2

公开(公告)日：2011-02-01

申请号：US11702552

申请日：2007-02-06

Applicant: Itsuo Watanabe ,  Kenzo Takemura ,  Akira Nagai ,  Kazuhiro Isaka ,  Osamu Watanabe ,  Kazuyoshi Kojima

Inventor： Itsuo Watanabe ,  Kenzo Takemura ,  Akira Nagai ,  Kazuhiro Isaka ,  Osamu Watanabe ,  Kazuyoshi Kojima

IPC: B32B27/38

CPC classification number: H01L24/83 ,  C09J9/02 ,  H01L23/49883 ,  H01L24/29 ,  H01L24/90 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0271 ,  H05K3/323 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0379 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T156/10 ,  Y10T156/109 ,  Y10T428/24942 ,  Y10T428/24959 ,  Y10T428/2852 ,  Y10T428/31511 ,  Y10T428/31515 ,  Y10T428/31855 ,  H01L2924/00

Abstract: An adhesive for bonding and securing a semiconductor chip to a circuit board and electrically connecting the electrodes of the two, and containing an adhesive resin composition and an inorganic filler being contained in an amount of 10 to 200 parts by weight of 100 parts by weight of the adhesive resin composition.

Abstract translation: 一种用于将半导体芯片接合并固定到电路板并电连接两个电极的粘合剂，并且包含粘合剂树脂组合物和无机填料，其含量为10至200重量份，100重量份的100重量份 粘合剂树脂组合物。

公开(公告)号：US07851921B2

公开(公告)日：2010-12-14

申请号：US11830505

申请日：2007-07-30

Applicant: Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

Inventor： Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

IPC: H01L23/48

CPC classification number: H05K3/305 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/0262 ,  H05K1/056 ,  H05K1/141 ,  H05K1/183 ,  H05K3/107 ,  H05K3/4614 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/1189 ,  Y02P70/613 ,  Y10T29/49155

Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer. The first and second conductive parts form connecting areas in the insulating layer, thereby connecting the first and second circuit substrates electrically.

Abstract translation: 为了减少设置在芯基板上的电路基板与要安装在其上的电路之间的连接缺陷，从而提高作为多层器件安装基板的可靠性。 装置安装基板包括：由基板，形成在该基板上的绝缘层和形成在该绝缘层上的第一导电层（包括导电部分）构成的第一电路基板; 以及安装在第一电路基板上的第二电路基板，由基底，形成在基底的底部的第二导电层（包括导电部）和形成在基底的顶部的第三导电层 的基地。 这里，第一和第二电路基板通过压力接合，使得第一和第二导电部件层叠并嵌入到绝缘层中。 第一和第二导电部分形成绝缘层中的连接区域，从而电连接第一和第二电路基板。

公开(公告)号：US20100299920A1

公开(公告)日：2010-12-02

申请号：US12856168

申请日：2010-08-13

Applicant: Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

Inventor： Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

IPC: H05K3/10

CPC classification number: H05K3/305 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/0262 ,  H05K1/056 ,  H05K1/141 ,  H05K1/183 ,  H05K3/107 ,  H05K3/4614 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/1189 ,  Y02P70/613 ,  Y10T29/49155

Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer. The first and second conductive parts form connecting areas in the insulating layer, thereby connecting the first and second circuit substrates electrically.

Abstract translation: 为了减少设置在芯基板上的电路基板与要安装在其上的电路之间的连接缺陷，从而提高作为多层器件安装基板的可靠性。 装置安装基板包括：由基板，形成在该基板上的绝缘层和形成在该绝缘层上的第一导电层（包括导电部分）构成的第一电路基板; 以及安装在第一电路基板上的第二电路基板，由基底，形成在基底的底部上的第二导电层（包括导电部）和形成在基底的顶部的第三导电层 的基地。 这里，第一和第二电路基板通过压力接合，使得第一和第二导电部件层叠并嵌入到绝缘层中。 第一和第二导电部分形成绝缘层中的连接区域，从而电连接第一和第二电路基板。

公开(公告)号：US20100230475A1

公开(公告)日：2010-09-16

申请号：US12787527

申请日：2010-05-26

Applicant: Stephen Leslie Buchwalter ,  Bruce K. Furman ,  Peter A. Gruber ,  Jae-Woong Nah ,  Da-Yuan Shih

Inventor： Stephen Leslie Buchwalter ,  Bruce K. Furman ,  Peter A. Gruber ,  Jae-Woong Nah ,  Da-Yuan Shih

IPC: B23K31/02

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/28 ,  H01L24/31 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/11822 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10242 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49165 ,  H01L2224/45111 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.