公开(公告)号：US20150130084A1

公开(公告)日：2015-05-14

申请号：US14246302

申请日：2014-04-07

Applicant: CHIPMOS TECHNOLOGIES INC.

Inventor： TSUNG JEN LIAO

IPC: H01L23/00 ,  H01L21/306 ,  H01L23/36

CPC classification number: H01L21/30604 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L29/0657 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11418 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/10158 ,  H05K1/111 ,  H05K2201/09436 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11

Abstract: A fan-out package structure including a heat radiating side edge that includes a semiconductor substrate; a bond pad located on the semiconductor substrate; and a redistribution layer connected with the bond pad and located on the semiconductor substrate, wherein an end of the redistribution layer extends to a sidewall of the semiconductor substrate, and the end is coplanar with the sidewall.

Abstract translation: 一种包括散热侧边缘的扇出封装结构，包括半导体衬底; 位于所述半导体衬底上的接合焊盘; 以及再结合层，其与所述接合焊盘连接并且位于所述半导体衬底上，其中所述再分布层的端部延伸到所述半导体衬底的侧壁，并且所述端部与所述侧壁共面。

公开(公告)号：US08819933B2

公开(公告)日：2014-09-02

申请号：US12957431

申请日：2010-12-01

Applicant: Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

Inventor： Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter

IPC: H01R43/02

CPC classification number: H01L24/10 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/112 ,  H05K2201/0769 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/0979 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49179 ,  H01L2924/00

Abstract: A method for forming an electrical structure. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.

Abstract translation: 一种形成电结构的方法。 电结构包括互连结构和衬底。 衬底包括导电焊盘和电连接到导电焊盘的多个导线迹线。 导电焊盘电连接和机械连接到互连结构。 多条导线包括第一线迹线，第二线迹线，第三线迹线和第四线迹线。 第一线迹和第二线迹均电连接到导电垫的第一侧。 第三线迹电连接到导电垫的第二侧。 第四线迹电连接到所述第一导电焊盘的第三侧。 多个导线配置成分布电流。

公开(公告)号：US08766103B2

公开(公告)日：2014-07-01

申请号：US12343784

申请日：2008-12-24

Applicant: Takeo Takahashi ,  Xiaoyu Mi ,  Tsuyoshi Yokoyama ,  Tokihiro Nishihara ,  Satoshi Ueda

Inventor： Takeo Takahashi ,  Xiaoyu Mi ,  Tsuyoshi Yokoyama ,  Tokihiro Nishihara ,  Satoshi Ueda

IPC: H05K1/02

CPC classification number: H05K1/16 ,  H01L2224/16 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/246 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2201/09436

Abstract: An electronic component includes: a multilayer ceramic substrate that has a penetration electrode formed therein, and has a passive element provided on the upper face thereof; an insulating film that is provided on the multilayer ceramic substrate, and has an opening above the penetration electrode; a first connecting terminal that is provided on the insulating film so as to cover the opening, and is electrically connected to the penetration electrode; and a second connecting terminal that is provided on a region of the insulating film other than the opening region.

Abstract translation: 电子部件包括：多层陶瓷基板，其具有形成在其中的穿透电极，并且在其上表面上设置无源元件; 绝缘膜，设置在所述多层陶瓷基板上，并且在所述贯通电极的上方具有开口部; 第一连接端子，设置在绝缘膜上以覆盖开口，并且电连接到穿透电极; 以及第二连接端子，其设置在除了开口区域之外的绝缘膜的区域上。

公开(公告)号：US08642899B2

公开(公告)日：2014-02-04

申请号：US12908518

申请日：2010-10-20

Applicant: Toshiji Hamatani ,  Tomoyuki Aoki ,  Hiroki Adachi ,  Hiroyuki Yajima

Inventor： Toshiji Hamatani ,  Tomoyuki Aoki ,  Hiroki Adachi ,  Hiroyuki Yajima

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/4007 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3164 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H05K1/095 ,  H05K1/113 ,  H05K3/245 ,  H05K3/281 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2203/063 ,  Y10T29/49165 ,  Y10T156/10 ,  H01L2924/00

Abstract: A method for manufacturing an electronic device comprising a terminal provided with a conductor which penetrates a cured prepreg is provided. At least one opening is formed in the prepreg. The prepreg is attached to a substrate over which an electronic element is formed so that the conductor included in the terminal overlaps with the opening. A conductive paste is provided in a region of the prepreg where the opening is provided. Part of the conductive paste flows into the opening to be in contact with the conductor included in the terminal. Then, heat treatment is performed so that the conductive paste and the prepreg are cured. In the process for manufacturing the terminal, it is not necessary to perform a step of forming an opening with a laser beam after the prepreg is cured. Thus, an adverse effect of a laser beam on the electronic element can be eliminated.

Abstract translation: 提供一种电子设备的制造方法，其包括设置有穿透固化的预浸料的导体的端子。 在预浸料坯中形成至少一个开口。 预浸料被附着到形成有电子元件的基板上，使得包含在端子中的导体与开口重叠。 在设置有开口部的预浸料坯的区域设置导电性糊剂。 导电膏的一部分流入开口以与终端中包括的导体接触。 然后，进行热处理，使得导电膏和预浸料固化。 在端子的制造方法中，在预浸料固化后，不必进行用激光形成开口的工序。 因此，可以消除激光束对电子元件的不良影响。

公开(公告)号：US20140000946A1

公开(公告)日：2014-01-02

申请号：US13927554

申请日：2013-06-26

Applicant: KYOCERA SLC Technologies Corporation

Inventor： Yoshihiro HOSOI ,  Takayuki TAGUCHI ,  Hidetoshi YUGAWA

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/09436 ,  H05K2201/09736 ,  H05K2201/099 ,  H05K2201/1034 ,  H05K2201/10674

Abstract: A wiring board according to the present invention includes an insulating board; a first pad provided inwardly from a surface of the insulating board and electrically connected to an electrode of an electronic component; a second pad provided on the surface of the insulating board and electrically connected to a lead terminal. The first pad and the second pad include a first layer region made of copper and a second layer region arranged on the first layer region and made of nickel, and a thickness of the second layer region of the second pad is larger than a thickness of the second layer region of the first pad.

Abstract translation: 根据本发明的布线板包括绝缘板; 从绝缘板的表面向内设置并电连接到电子部件的电极的第一焊盘; 第二焊盘，设置在绝缘板的表面上并电连接到引线端子。 第一焊盘和第二焊盘包括由铜制成的第一层区域和布置在第一层区域上并由镍制成的第二层区域，并且第二焊盘的第二层区域的厚度大于 第一垫的第二层区域。

公开(公告)号：US20130335940A1

公开(公告)日：2013-12-19

申请号：US14002346

申请日：2012-03-01

Applicant: Takashi Matsui ,  Motoji Shiota ,  Hiroki Nakahama

Inventor： Takashi Matsui ,  Motoji Shiota ,  Hiroki Nakahama

IPC: H05K1/18

CPC classification number: H05K1/18 ,  G02F1/13454 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10165 ,  H01L2224/13013 ,  H01L2224/13144 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/16237 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81903 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2924/07802 ,  H01L2924/15788 ,  H01L2924/351 ,  H05K1/111 ,  H05K2201/09436 ,  H05K2201/09709 ,  H05K2201/09745 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A wiring substrate (11) includes: a substrate; and, formed upon the substrate, a plurality of wiring lines, a plurality of circuit elements, and a plurality of connecting terminals (51) connected via the plurality of wiring lines. Each of the plurality of connecting terminals (51) includes a pair of protrusion parts (50), forming a depression part (60) between the pair of protrusion parts (50), and a depression electrode (52) that is disposed in the depression part (60) and that at least partially covers each protrusion of the pair of protrusion parts (50).

Abstract translation: 布线基板（11）包括：基板; 并且在所述基板上形成有多条布线，多个电路元件以及经由所述多根布线连接的多个连接端子（51）。 多个连接端子（51）中的每一个包括在一对突出部（50）之间形成有凹部（60）的一对突出部（50），设置在该凹部 部分（60）并且至少部分地覆盖所述一对突出部分（50）中的每个突起。

公开(公告)号：US08377506B2

公开(公告)日：2013-02-19

申请号：US12574350

申请日：2009-10-06

Applicant: Chih-Cheng Lee

Inventor： Chih-Cheng Lee

IPC: B05D5/12 ,  C25D5/02 ,  C23C14/00

CPC classification number: H05K3/4007 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/112 ,  H05K3/243 ,  H05K3/42 ,  H05K2201/0352 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A substrate structure is provided. The substrate structure includes a substrate, a first insulation layer, a conductive part, a second insulation layer, a seed layer and a conductive layer. The substrate has a first circuit pattern layer and a second circuit pattern layer, which are located on two opposite surfaces of the substrate respectively. The first insulation layer formed on the first circuit pattern layer has a first insulation hole, which exposes a first opening in the outer surface of the first insulation layer. The conductive part formed on the first insulation hole for electrically connecting with a chip is enclosed by the edge of the first opening. The second insulation layer formed on the second circuit pattern layer has a second insulation hole in which the seed layer is formed. The conductive layer is formed on the seed layer for electrically connecting with a circuit board.

Abstract translation: 提供了基板结构。 基板结构包括基板，第一绝缘层，导电部件，第二绝缘层，种子层和导电层。 衬底具有分别位于衬底的两个相对表面上的第一电路图案层和第二电路图案层。 形成在第一电路图案层上的第一绝缘层具有第一绝缘孔，其暴露第一绝缘层的外表面中的第一开口。 形成在与芯片电连接的第一绝缘孔上的导电部分被第一开口的边缘包围。 形成在第二电路图案层上的第二绝缘层具有形成种子层的第二绝缘孔。 导电层形成在种子层上，用于与电路板电连接。

公开(公告)号：US20130029458A1

公开(公告)日：2013-01-31

申请号：US13627312

申请日：2012-09-26

Applicant: HYNIX SEMICONDUCTOR INC.

Inventor： Woong Sun LEE

IPC: H01L21/60

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/247 ,  H05K3/3457 ,  H05K2201/035 ,  H05K2201/09436 ,  H01L2924/00

Abstract: A substrate for a semiconductor package includes a ball land disposed on one surface of an insulating layer. A solder resist is applied to the surface of insulating layer while leaving the ball land exposed. A coating film is applied on the exposed surface of the ball land. The coating film includes a high molecular compound having metal particles. In the substrate having the ball land with the coating film formed thereon, it is not necessary to subject the substrate to a UBM formation process.

Abstract translation: 用于半导体封装的衬底包括设置在绝缘层的一个表面上的球形区域。 在绝缘层的表面上施加阻焊剂，同时露出球场。 将涂膜施加在球面的暴露表面上。 涂膜包括具有金属颗粒的高分子化合物。 在其上形成有涂膜的球面的基板中，不需要使基板进行UBM形成工艺。

公开(公告)号：US20130025926A1

公开(公告)日：2013-01-31

申请号：US13644667

申请日：2012-10-04

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung ,  Wei-Cheng Chen

IPC: H05K1/11

CPC classification number: H05K3/4007 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit substrate having a base layer, a patterned conductive layer, a dielectric layer and a conductive block is provided. The patterned conductive layer is disposed on the base layer and having an inner pad. The dielectric layer is disposed on the base layer and covering the patterned conductive layer. The conductive block penetrates the dielectric layer, the conductive block being substantially coplanar with the dielectric layer and connecting the inner pad.

Abstract translation: 提供具有基底层，图案化导电层，电介质层和导电块的电路基板。 图案化导电层设置在基底层上并具有内部衬垫。 电介质层设置在基底层上并覆盖图案化的导电层。 导电块穿透电介质层，导电块基本上与电介质层共面并连接内焊盘。

公开(公告)号：US20120061347A1

公开(公告)日：2012-03-15

申请号：US13273335

申请日：2011-10-14

Applicant: Satoru KAWAI ,  Kenji Sakai ,  Liyi Chen

Inventor： Satoru KAWAI ,  Kenji Sakai ,  Liyi Chen

IPC: H05K3/46

CPC classification number: H05K3/4007 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/205 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09436 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49213 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for manufacturing a printed wiring board including preparing a carrier, forming a metal layer on the carrier, forming an etching resist on the metal layer, forming a metal film from the metal layer underneath the resist by removing portion of the metal layer exposed through the resist and part of the metal layer contiguous to the portion of the metal layer and underneath the resist, forming a coating layer on side surface of the film and the carrier, forming a pad on the coating layer, removing the resist, forming a resin insulation layer on the film and surface of the pad, forming an opening reaching the surface of the pad in the insulation layer, forming a conductive circuit on the insulation layer, forming a via conductor connecting the circuit and the pad in the opening, removing the carrier from the film and coating layer, and removing the film.

Abstract translation: 一种制造印刷电路板的方法，包括制备载体，在载体上形成金属层，在金属层上形成抗蚀剂，在抗蚀剂下面的金属层形成金属膜，除去暴露于金属层的部分 所述抗蚀剂和所述金属层的与所述金属层的所述部分相邻并且在所述抗蚀剂下方的部分，在所述膜和载体的侧表面上形成涂层，在所述涂层上形成焊盘，除去所述抗蚀剂，形成树脂 在所述膜的表面和所述垫的表面上形成绝缘层，形成在所述绝缘层中到达所述焊盘表面的开口，在所述绝缘层上形成导电电路，形成在所述开口中连接所述电路和所述焊盘的通孔导体， 载体从膜和涂层，并去除膜。