公开(公告)号：US20030178229A1

公开(公告)日：2003-09-25

申请号：US10257370

申请日：2003-05-07

Inventor： Yukihiko Toyoda ,  Yoichiro Kawamura ,  Tomoyuki Ikeda

IPC: H05K001/11 ,  H01R012/04

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/116 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/068 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09745 ,  H01L2924/00

Abstract: An object of the present invention is to provide a multilayered printed circuit board having a short wiring distance of the conductor circuits, wide option of the design of the conductor circuits and additionally excellent in reliability since cracking scarcely takes place in the interlaminar resin insulating layers in the vicinity of via-holes. The present invention is a multilayered printed circuit board comprising: a conductor circuit and an interlaminar resin insulating layer serially formed on a substrate in alternate fashion and in repetition, wherein a connection of the conductor circuits through the interlaminar resin insulating layers is performed by a via-hole, wherein via-holes in different level layers among the via-holes are formed so as to form a stack-via structure, and wherein at least one of the land diameters of the above-mentioned via-holes in different level layers having the stack via structure is different from the land diameters of other via-holes.

Abstract translation: 本发明的目的是提供一种具有导体电路的布线距离短的多层印刷电路板，可广泛选择导体电路的设计，并且由于在层间树脂绝缘层中几乎不发生破裂 通孔附近。 本发明是一种多层印刷电路板，包括：导体电路和层间树脂绝缘层，其以交替的方式和重复地串联形成在基板上，其中通过层间树脂绝缘层的导体电路的连接通过通孔 孔，其中形成通孔中的不同级别的通孔，以形成堆叠通孔结构，并且其中不同层级中的上述通孔的平台直径中的至少一个具有 堆叠通孔结构不同于其它通孔的焊盘直径。

公开(公告)号：US06392164B1

公开(公告)日：2002-05-21

申请号：US09417662

申请日：1999-10-14

Applicant: Hideki Iwaki ,  Yutaka Taguchi ,  Tetsuyoshi Ogura

Inventor： Hideki Iwaki ,  Yutaka Taguchi ,  Tetsuyoshi Ogura

IPC: H05K111

CPC classification number: H05K1/0251 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/024 ,  H05K1/0298 ,  H05K1/116 ,  H05K2201/0715 ,  H05K2201/09454 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2201/09881 ,  H01L2924/00

Abstract: An insulator is provided between interconnect layers oppositely placed. The interconnect layers are connected between by connection members provided through the insulator. The connection members at one and the other ends are connected between in their center positions. A shield layer is provided spaced from the intermediate connection layer generally on a same plane as the intermediate connection layer. The interconnect layers where considered generally as a circular cylinder have a diameter m, and the intermediate connection layer where considered generally as circular has a diameter r, r

Abstract translation: 在相互布置的互连层之间设置绝缘体。 互连层通过通过绝缘体提供的连接构件连接在一起。 连接构件在一端和另一端连接在它们的中心位置之间。 屏蔽层设置成与中间连接层间隔开，通常在与中间连接层相同的平面上。 通常被认为是圆柱体的互连层具有直径m，并且被认为通常为圆形的中间连接层具有直径r，r

公开(公告)号：US06342682B1

公开(公告)日：2002-01-29

申请号：US09633881

申请日：2000-08-07

Applicant: Yoji Mori ,  Yoichiro Kawamura

Inventor： Yoji Mori ,  Yoichiro Kawamura

IPC: H01R909

CPC classification number: H05K1/116 ,  H05K1/0201 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/09881 ,  Y10T29/49126 ,  Y10T428/24917

Abstract: A printed wiring board in which an opening existing around a pad which is a photovia land is arranged so that it is not overlapped with the pad, the area of an opening existing around a pad and that of another opening are equalized, the quantity of resin which is filled in each opening or is equalized throughout a printed wiring board and the quantity of resin overflowing from each opening or when resin is filled in each opening or is uniformed is provided. According to such a printed wiring board, a reliable printed wiring board wherein secure connection is enabled without causing disconnection can be realized when a circuit pattern provided on an interlayer insulating board formed on the printed wiring board and a conductor pad are connected by arranging an opening existing around a conductor pad so that it is not overlapped with the conductor pad and substantially equalizing the quantity of resin which is filled in an opening around a conductor pad and that of resin which is filled in another opening.

Abstract translation: 印刷电路板，其中存在于作为光电极区域的焊盘周围的开口布置成使得其不与焊盘重叠，存在于焊盘周围的开口的面积和另一个开口的开口面积相等，树脂的量 填充在每个开口中或在整个印刷线路板上均匀化，并且提供从每个开口溢出的树脂或当在每个开口中填充树脂或均匀化时的树脂量。 根据这样的印刷电路板，当通过布置开口来连接设置在形成在印刷线路板上的层间绝缘板上的电路图案和导体焊盘时，可以实现可靠的印刷布线板，其中不会导致断开而实现安全连接， 存在于导体焊盘周围，使得其不与导体焊盘重叠，并且基本上均匀地填充在导体焊盘周围的开口中的树脂的量和填充在另一个开口中的树脂的量。

公开(公告)号：US20010054938A1

公开(公告)日：2001-12-27

申请号：US09816889

申请日：2001-03-23

Inventor： Charles A. Miller

IPC: H01P001/04

CPC classification number: H05K1/025 ,  H01L2224/48091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H03H7/0115 ,  H03H7/38 ,  H03H2001/0085 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/113 ,  H05K1/116 ,  H05K1/162 ,  H05K3/3421 ,  H05K3/429 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/10689 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An interconnect system for linking integrated circuits (ICs) mounted on a surface of a printed circuit board (PCB) includes a trace positioned below the surface, one or more vias linking the trace to the surface of the PCB, and other conductors linking pads on the ICs to the vias. Impedances of the various components of the interconnect system are sized relative to one another to optimize interconnect system frequency response.

Abstract translation: 用于连接安装在印刷电路板（PCB）表面上的集成电路（IC）的互连系统包括位于表面下方的迹线，将迹线连接到PCB的表面的一个或多个通孔以及将PCB上的其它导体连接到 IC到通孔。 互连系统的各种组件的阻抗相对于彼此大小，以优化互连系统的频率响应。

公开(公告)号：US06323439B1

公开(公告)日：2001-11-27

申请号：US09386334

申请日：1999-08-31

Applicant: Rokuro Kambe ,  Toru Matsuura

Inventor： Rokuro Kambe ,  Toru Matsuura

IPC: H01R909

CPC classification number: H05K3/429 ,  H05K3/0038 ,  H05K3/44 ,  H05K3/4608 ,  H05K2201/09454 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/09736 ,  H05K2201/09745 ,  Y10T29/49165

Abstract: A multilayer resin wiring board includes a metal core substrate having a first main surface and a second main surface; a plurality of wiring layers located on the first and second main surfaces of the metal core substrate; a plurality of insulating resin layers, each intervening between the metal core substrate and the wiring layers and between the metal core substrate and the wiring layers and between the wiring layers; and a via formed on the wall of a through hole for connection to the metal core substrate extending through the insulating resin layers and the metal core substrate so as to establish electrical conductivity to the metal core substrate. The metal core substrate has a thin portion which is thinner than the remaining portion of the metal core substrate. The through hole for connection to the metal core substrate is formed through the thin portion by laser machining.

Abstract translation: 多层树脂配线板包括具有第一主表面和第二主表面的金属芯基板; 位于金属芯基板的第一和第二主表面上的多个布线层; 多个绝缘树脂层，各自介于金属芯基板和布线层之间，金属芯基板和布线层之间以及布线层之间; 以及形成在通孔的壁上的通孔，用于连接到延伸穿过绝缘树脂层和金属芯基板的金属芯基板，以便建立对金属芯基板的导电性。 金属芯基板具有比金属芯基板的剩余部分薄的薄部。 用于连接到金属芯基板的通孔通过激光加工形成在薄部分上。

公开(公告)号：US06316738B1

公开(公告)日：2001-11-13

申请号：US08894342

申请日：1997-08-26

Applicant: Yoji Mori ,  Yoichiro Kawamura

Inventor： Yoji Mori ,  Yoichiro Kawamura

IPC: H01R909

CPC classification number: H05K1/116 ,  H05K1/0201 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/09881 ,  Y10T29/49126 ,  Y10T428/24917

Abstract: A printed wiring board in which an opening existing around a pad which is a photovia land is arranged so that it is not overlapped with the pad, the area of an opening existing around a pad and that of another opening are equalized, the quantity of resin which is filled in each opening or is equalized throughout a printed wiring board and the quantity of resin overflowing from each opening or when resin is filled in each opening or is uniformed is provided. According to such a printed wiring board, a reliable printed wiring board wherein secure connection is enabled without causing disconnection can be realized when a circuit pattern provided on an interlayer insulating board formed on the printed wiring board and a conductor pad are connected by arranging an opening existing around a conductor pad so that it is not overlapped with the conductor pad and substantially equalizing the quantity of resin which is filled in an opening around a conductor pad and that of resin which is filled in another opening.

Abstract translation: 印刷电路板，其中存在于作为光电极区域的焊盘周围的开口布置成使得其不与焊盘重叠，存在于焊盘周围的开口的面积和另一个开口的开口面积相等，树脂的量 填充在每个开口中或在整个印刷线路板上均匀化，并且提供从每个开口溢出的树脂或当在每个开口中填充树脂或均匀化时的树脂量。 根据这样的印刷电路板，当通过布置开口来连接设置在形成在印刷线路板上的层间绝缘板上的电路图案和导体焊盘时，可以实现可靠的印刷布线板，其中不会导致断开而实现安全连接， 存在于导体焊盘周围，使得其不与导体焊盘重叠，并且基本上均匀地填充在导体焊盘周围的开口中的树脂的量和填充在另一个开口中的树脂的量。

公开(公告)号：US6083340A

公开(公告)日：2000-07-04

申请号：US124692

申请日：1998-07-29

Applicant: Kazuo Nomura ,  Ichiro Ishiyama ,  Koji Higashi ,  Masaki Kato ,  Ichiro Nagare ,  Hiroyuki Kurokawa ,  Yozo Ohara

Inventor： Kazuo Nomura ,  Ichiro Ishiyama ,  Koji Higashi ,  Masaki Kato ,  Ichiro Nagare ,  Hiroyuki Kurokawa ,  Yozo Ohara

IPC: H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  B32B31/20

CPC classification number: H05K3/4069 ,  H05K3/429 ,  B32B2457/08 ,  H05K2201/0257 ,  H05K2201/035 ,  H05K2201/09454 ,  H05K2201/09981 ,  H05K2203/1476 ,  H05K3/4611 ,  Y10T156/1057 ,  Y10T29/49165

Abstract: A multi-layer circuit board capable of reducing an electrical resistance between circuit patterns positioned inside the circuit board and a through-hole connection conductor. A plurality of circuit patterns are superposed on each other with a plurality of insulating layers being alternately interposed therebetween in turn. A solution in which ultrafine metal particles of the independent dispersion type such as silver, gold, palladium or the like are contained in a colloid-like manner is applied so as to extend from one of lands through an inner surface of a through-hole to the other land. Then, the solution is calcined to form a metal particle film, The metal particle film is coated thereon with a conductive paste such as a resin/silver paste or the like, which is then calcined to form a conductive paste layer.

Abstract translation: 一种能够减小位于电路板内部的电路图案与通孔连接导体之间的电阻的多层电路板。 多个电路图案彼此重叠，并且依次交替插入多个绝缘层。 以胶体状包含诸如银，金，钯等独立分散型的超细金属颗粒的溶液，以从一个区域延伸穿过通孔的内表面到 另一块土地。 然后，将溶液煅烧以形成金属颗粒膜。用诸如树脂/银浆等的导电浆料涂覆金属颗粒膜，然后将其煅烧以形成导电浆料层。

公开(公告)号：US5743004A

公开(公告)日：1998-04-28

申请号：US505076

申请日：1995-07-21

Applicant: Ivan Ivor Chobot ,  John Arthur Covert ,  Randy Lee Haight ,  Keith David Mansfield ,  Donald Wayne Miller ,  Reinaldo Anthony Neira ,  Alexander Petrovich ,  Paul Camilo Sviedrys ,  Louise Ann Tiemann ,  Gerald Arthur Valenta ,  Thurston Bryce Youngs, Jr.

Inventor： Ivan Ivor Chobot ,  John Arthur Covert ,  Randy Lee Haight ,  Keith David Mansfield ,  Donald Wayne Miller ,  Reinaldo Anthony Neira ,  Alexander Petrovich ,  Paul Camilo Sviedrys ,  Louise Ann Tiemann ,  Gerald Arthur Valenta ,  Thurston Bryce Youngs, Jr.

IPC: H01L23/12 ,  H05K1/02 ,  H05K1/11 ,  H05K3/22 ,  H05K3/34 ,  H05K3/42 ,  H05K3/46 ,  H05K3/36

CPC classification number: H05K1/0201 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/062 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K3/429 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49165

Abstract: A multi-layer printed circuit board or card including at least one passage in at least one of the layers of the circuit board or card for preventing the diffusion of heat throughout the circuit board or card during the securing or removal of components in plated through holes in the circuit board or card by the heating of the plating material to a temperature above a melting point of the plating material.

Abstract translation: 一种多层印刷电路板或卡，其包括在电路板或卡的至少一层中的至少一个通道，用于在固定或移除电镀通孔中的部件时防止热量扩散到整个电路板或卡 在电路板或卡中通过将电镀材料加热至高于电镀材料熔点的温度。

公开(公告)号：US4675789A

公开(公告)日：1987-06-23

申请号：US811355

申请日：1985-12-20

Applicant: Kiyoshi Kuwabara ,  Mikio Nishihara ,  Kazuhisa Tsunoi

Inventor： Kiyoshi Kuwabara ,  Mikio Nishihara ,  Kazuhisa Tsunoi

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/42 ,  H05K1/14

CPC classification number: H05K1/116 ,  H05K2201/09327 ,  H05K2201/09454 ,  H05K3/429

Abstract: A high density multilayer printed circuit board comprising generally parallel signal layers, electric source layers, and ground layers, with insulating layers arranged between the signal layers and the electric source layers, between the electric source layers and the ground layers, and between the ground layers and the signal layers respectively. Conductor portions are formed in through holes which are opened in a direction transverse to the signal layers, electric source layers, and ground layers. The conductor portions are electrically connected to the signal layers and/or the electric source layers, and/or the ground layers, through the lands thereof, the connections of the lands being substantially equally distributed among the conductor portions.

Abstract translation: 一种高密度多层印刷电路板，包括大致平行的信号层，电源层和接地层，绝缘层布置在信号层和电源层之间，电源层和接地层之间，以及接地层之间 和信号层。 导体部分形成在与信号层，电源层和接地层横向的方向上开放的通孔中。 导体部分通过其平台与信号层和/或电源层和/或接地层电连接，焊盘的连接基本上均匀分布在导体部分之间。

公开(公告)号：US11882656B2

公开(公告)日：2024-01-23

申请号：US17708486

申请日：2022-03-30

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Daisuke Minoura

IPC: H05K1/11 ,  H05K3/38 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/113 ,  H05K3/383 ,  H05K3/389 ,  H05K3/0035 ,  H05K3/428 ,  H05K2201/096 ,  H05K2201/09454 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/0723

Abstract: A wiring substrate includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on the insulating layer, a connection conductor penetrating through the insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer and adhering the first conductor layer and the insulating layer. The first conductor layer includes a conductor pad in contact with the connection conductor such that the conductor pad has a surface having a first region and a second region on second conductor layer side and that surface roughness of the first region is different from surface roughness of the second region, and the conductor pad of the first conductor layer is formed such that the first region is covered by the coating film and that the second region is covered by the connection conductor.