公开(公告)号：US07656166B2

公开(公告)日：2010-02-02

申请号：US12072703

申请日：2008-02-27

Applicant: Yoshiyuki Fukami

Inventor： Yoshiyuki Fukami

IPC: G01R31/02 ,  G01R27/26

CPC classification number: H05K1/0268 ,  G01R31/2805 ,  G01R31/2812 ,  H05K1/0306 ,  H05K3/4605 ,  H05K2201/09481 ,  H05K2201/09845

Abstract: A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. The ceramic substrate has an internal conductor layer, which is connected to a test pad. The first conductor layer is formed, and then an electric capacitance is measured between the test pad and a wiring pattern of the first conductor layer. On the other hand, an electrical capacitance is calculated under the normal wiring pattern condition. The measured value is compared to the calculated value to determine whether the wiring pattern is good or bad. Similar measurements and comparisons are carried out for each of the second through fifth conductor layers to determine whether a three-dimensional wiring path is good or bad. As the ceramic substrate has an internal conductor layer, the electric capacitance of the wiring can be measured without an overall grounded layer in the multilayer wiring section, which is a characteristic part different from others among a variety of the multilayer wiring boards.

Abstract translation: 多层布线基板具有形成有多层布线部的陶瓷基板。 陶瓷基板具有连接到测试垫的内部导体层。 形成第一导体层，然后在测试焊盘和第一导体层的布线图案之间测量电容。 另一方面，在正常布线图案条件下计算电容。 将测量值与计算值进行比较，以确定布线图案是好还是坏。 对于第二至第五导体层中的每一个执行类似的测量和比较，以确定三维布线路径是好还是坏。 由于陶瓷基板具有内部导体层，所以可以在多层布线部中没有整体接地层来测量布线的电容，这是各种多层布线板中与其他布线板不同的特征部分。

公开(公告)号：US20090315856A1

公开(公告)日：2009-12-24

申请号：US12485624

申请日：2009-06-16

Applicant: Harutoshi OIKAWA ,  Kiyohiro KIMURA

Inventor： Harutoshi OIKAWA ,  Kiyohiro KIMURA

IPC: G06F3/045 ,  H05K1/02

CPC classification number: H05K3/361 ,  G06F3/045 ,  H05K3/281 ,  H05K3/323 ,  H05K3/421 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/097 ,  H05K2201/0979 ,  H05K2203/1572

Abstract: A flexible printed circuit includes: a first wiring layer and a second wiring layer being in contact with one surface of a flexible substrate, a third wiring layer and a fourth wiring layer on the other surface of the flexible substrate, a first conductive member being formed on surfaces in proximity to a through hole of the second wiring layer and the fourth wiring layer; a second conductive member being formed on surfaces in proximity to the first end section of the first wiring layer and the third wiring layer; and an insulating layer being formed in a space between the first wiring layer and the second conductive member, and the second wiring layer and the first conductive member and a space between the third wiring layer and the second conductive member, and the fourth wiring layer and the first conductive member.

Abstract translation: 柔性印刷电路包括：第一布线层和与柔性基板的一个表面接触的第二布线层，在柔性基板的另一个表面上的第三布线层和第四布线层，形成第一导电部件 在第二布线层和第四布线层的通孔附近的表面上; 第二导电构件形成在靠近第一布线层和第三布线层的第一端部的表面上; 以及在所述第一布线层和所述第二导电构件之间的空间中形成绝缘层，以及所述第二布线层和所述第一导电构件以及所述第三布线层和所述第二导电构件之间的空间，以及所述第四布线层和 第一导电构件。

公开(公告)号：US07626208B2

公开(公告)日：2009-12-01

申请号：US11309200

申请日：2006-07-13

Applicant: Chien-Cheng Yang ,  Chao-Kai Hsu ,  Jing-Yao Chang

Inventor： Chien-Cheng Yang ,  Chao-Kai Hsu ,  Jing-Yao Chang

IPC: H01L33/00

CPC classification number: H05K1/0203 ,  F21K9/00 ,  F21V33/0008 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L2924/0002 ,  H05K1/189 ,  H05K2201/09318 ,  H05K2201/09481 ,  H05K2201/10106 ,  H05K2201/10553 ,  H05K2203/049 ,  H01L2924/00

Abstract: A bendable LED planar light source structure, a flexible substrate therefore, and a manufacturing method thereof are provided. The flexible substrate has metal layers on both sides, where the metal layer on one side has a circuit layout, and the metal layer on the other side has a pattern structure or a whole metal coating with reflecting and scattering characteristics. Meanwhile, bonding pads are provided on the same side or opposite side as the metal layer with the circuit layout, and an array of LED dies is bonded with the bonding pads through wire bonding or flip chip bonding, such that the LED dies are conducted with current through the circuit layout on the flexible substrate, so as to form a planar light source.

Abstract translation: 提供了一种可弯曲的LED平面光源结构，因此可挠性基板及其制造方法。 柔性基板的两侧具有金属层，其一侧的金属层具有电路布局，另一侧的金属层具有具有反射和散射特性的图案结构或整体金属涂层。 同时，在具有电路布局的金属层的相同侧或相对侧上设置接合焊盘，并且通过引线接合或倒装芯片接合将LED管芯阵列与接合焊盘接合，使得LED管芯与 电流通过柔性基板上的电路布局，以形成平面光源。

公开(公告)号：US07614142B2

公开(公告)日：2009-11-10

申请号：US12068272

申请日：2008-02-05

Applicant: Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

IPC: H05K3/36 ,  H01L23/29

CPC classification number: H01L23/50 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599

Abstract: A method for fabricating an interposer includes: forming on one primary surface of a first substrate a thin-film capacitor including a first capacitor electrode, a crystalline capacitor dielectric film formed on the first electrode and a second capacitor electrode formed on the dielectric film; and forming on the primary surface of the first substrate and the capacitor a first layer as semi-cured, and a first partial electrode to be a part of a through-electrode, buried in the first resin layer and electrically connected to the first electrode or the second electrode. The method further includes cutting an upper part of the first partial electrode and an upper part of the first resin layer with a cutting tool; forming on one primary surface of a second substrate a second resin layer as semi-cured, and a second partial electrode to be a part of the through-electrode, buried in the second resin layer and disposed in alignment with the first partial electrode; cutting an upper part of the second partial electrode and an upper part of the second resin layer with a cutting tool; making thermal processing with the first resin layer and the second resin layer in close contact with each other to adhere the first resin and the second resin layer to each other while jointing the first and second partial electrodes to each other; removing the first substrate; forming on said one primary surface of the second substrate a third resin layer, covering the thin-film capacitor, burying a third partial electrode to be a part of the through-electrode in the third resin layer, supporting the third resin layer by a supporting substrate; and removing the second substrate.

Abstract translation: 一种用于制造插入件的方法，包括：在第一基板的一个主表面上形成薄膜电容器，薄膜电容器包括第一电容器电极，形成在第一电极上的晶体电容器电介质膜和形成在电介质膜上的第二电容器电极; 并且在第一基板和电容器的主表面上形成半固化的第一层，以及作为通孔的一部分的第一部分电极，埋入第一树脂层中并电连接到第一电极或 第二电极。 该方法还包括用切割工具切割第一部分电极的上部和第一树脂层的上部; 在第二基板的一个主表面上形成半固化的第二树脂层和作为所述通孔的一部分的第二部分电极，所述第二部分电极埋入所述第二树脂层中并与所述第一部分电极对准; 用切割工具切割第二部分电极的上部和第二树脂层的上部; 使第一树脂层和第二树脂层彼此紧密接触进行热处理，以将第一和第二部分电极彼此接合，使第一树脂和第二树脂层彼此粘合; 去除第一衬底; 在所述第二基板的所述一个主表面上形成覆盖所述薄膜电容器的第三树脂层，在所述第三树脂层中埋设作为所述贯通电极的一部分的第三部分电极，通过支撑所述第三树脂层 基质; 并移除第二基板。

公开(公告)号：US20090250255A1

公开(公告)日：2009-10-08

申请号：US12080311

申请日：2008-04-02

Applicant: Thomas H. Shilling ,  Todd Snider ,  Melissa Grupen-Shemansky

Inventor： Thomas H. Shilling ,  Todd Snider ,  Melissa Grupen-Shemansky

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L23/50 ,  H01L23/5383 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/107 ,  H01L2924/3011 ,  H05K2201/09227 ,  H05K2201/09481 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: In the present electronic structure, a substrate is provided in the form of a circuit board. First and second electronic devices are positioned on opposite sides of the circuit board, each having a plurality of contacts connected to the circuit board. Each of the contacts of the first device is connected to a contact of the second device by a connector though the circuit board. At least one of the contacts of the first device is connected to the contact of the second device which is most adjacent to that contact of the first device across the circuit board.

Abstract translation: 在本电子结构中，以电路板的形式设置基板。 第一和第二电子设备位于电路板的相对侧上，每个具有连接到电路板的多个触点。 第一装置的每个触点通过连接器通过电路板连接到第二装置的触点。 第一装置的至少一个触点连接到第二装置的与第一装置的该触点最相邻的触点跨过电路板。

公开(公告)号：US20090236139A1

公开(公告)日：2009-09-24

申请号：US12051133

申请日：2008-03-19

Applicant: Anders P. PEDERSEN ,  Daniel A. ROBISON

Inventor： Anders P. PEDERSEN ,  Daniel A. ROBISON

IPC: H05K1/11 ,  H05K3/36

CPC classification number: H05K1/144 ,  H05K1/0219 ,  H05K1/111 ,  H05K1/117 ,  H05K1/142 ,  H05K3/301 ,  H05K3/366 ,  H05K3/403 ,  H05K2201/09145 ,  H05K2201/0919 ,  H05K2201/09481 ,  H05K2201/09809 ,  H05K2201/10446

Abstract: A method is for making a printed wiring board (PWB) assembly. The method may include forming a first PWB having a plurality of first electrically conductive pads, forming a second PWB including a plurality of electrically conductive traces having exposed ends on an edge surface of the second PWB, and covering the edge surface of the second PWB with an electrically conductive layer. The method may also include selectively removing portions of the electrically conductive layer to define a plurality of second electrically conductive pads electrically connected to corresponding ones of the exposed ends of the electrically conductive traces, and assembling the first and second PWBs together so that the first and second electrically conductive pads are electrically coupled together to define the PWB assembly.

Abstract translation: 一种制造印刷电路板（PWB）组件的方法。 该方法可以包括形成具有多个第一导电焊盘的第一PWB，形成第二PWB，第二PWB包括在第二PWB的边缘表面上具有暴露端的多个导电迹线，并且用第二PWB的边缘表面覆盖第二PWB的边缘表面 导电层。 该方法还可以包括选择性地去除导电层的部分以限定电连接到导电迹线的相应的暴露端的多个第二导电焊盘，以及将第一和第二PWB组合在一起，使得第一和 第二导电焊盘电耦合在一起以限定PWB组件。

公开(公告)号：US20090236130A1

公开(公告)日：2009-09-24

申请号：US12216428

申请日：2008-07-03

Applicant: Jee Soo Mok ,  Je Gwang Yoo ,  Chang Sup Ryu

Inventor： Jee Soo Mok ,  Je Gwang Yoo ,  Chang Sup Ryu

IPC: H05K1/09 ,  H05K3/42

CPC classification number: H05K3/4608 ,  H05K1/056 ,  H05K3/445 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2203/0315 ,  Y10T29/49165

Abstract: Disclosed herein is a multilayered circuit board, including: a metal base layer including a metal layer formed through-holes, an insulating film formed on a surface of the metal layer, a first circuit layer having circuit patterns formed on one side of the metal layer and a second circuit layer having protruding connecting pads, formed on the other side of the metal layer; a build-up layer formed on the first circuit layer; and a solder resist layer. The multilayered printed circuit board is advantageous in that the thickness thereof is decreased and the bending strength and radiation characteristics thereof are improved.

Abstract translation: 本发明公开了一种多层电路板，包括：金属基层，包括金属层形成的通孔;绝缘膜，形成在金属层的表面上;第一电路层，具有形成在金属层一侧的电路图案 以及形成在所述金属层的另一侧的具有突出连接焊盘的第二电路层; 形成在第一电路层上的积聚层; 和阻焊层。 多层印刷电路板的优点在于其厚度降低，并且其弯曲强度和辐射特性得到改善。

公开(公告)号：US07553738B2

公开(公告)日：2009-06-30

申请号：US11609295

申请日：2006-12-11

Applicant: Yongki Min ,  Huankiat Seh

Inventor： Yongki Min ,  Huankiat Seh

IPC: H01L21/20

CPC classification number: H01G4/33 ,  H01G4/232 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L27/016 ,  H01L2924/0002 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2203/1184 ,  Y10S438/957 ,  Y10T29/41 ,  Y10T29/417 ,  Y10T29/43 ,  H01L2924/00

Abstract: A microelectronic device, a method of fabricating the device, and a system including the device. The method includes: providing a substrate including an underlying conductive layer and a polymer build-up layer overlying the underlying conductive layer; providing a passive microelectronic structure; embedding the passive structure in the polymer build-up layer of the substrate; and patterning the passive structure after embedding, patterning including over-etching the bottom electrode layer. The passive microelectronic structure being embedded includes an unpatterned bottom electrode layer; an unpatterned capacitor dielectric layer overlying the bottom electrode layer; and an unpatterned top electrode layer overlying the capacitor dielectric layer.

Abstract translation: 微电子器件，制造该器件的方法以及包括该器件的系统。 该方法包括：提供包括下面的导电层和覆盖在下面的导电层上的聚合物堆积层的衬底; 提供无源微电子结构; 将被动结构嵌入衬底的聚合物堆积层中; 并且在嵌入之后图案化被动结构，图案化包括对底部电极层进行过蚀刻。 嵌入的被动微电子结构包括未图案化的底电极层; 覆盖底部电极层的未图案化的电容器电介质层; 以及覆盖电容器介电层的未图案化的顶部电极层。

公开(公告)号：US07491896B2

公开(公告)日：2009-02-17

申请号：US12010004

申请日：2008-01-18

Applicant: John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

Inventor： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

IPC: H05K1/11

CPC classification number: H01L23/49811 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0256 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4641 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09481 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49176 ,  H01L2224/0401

Abstract: An information handling system, e.g., a mainframe computer, which includes as part thereof a housing having therein an electrical assembly including a circuitized substrate which in turn includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within the system. At least one electrical component is positioned on and electrically coupled to the circuitized substrate of the system's electrical assembly.

Abstract translation: 一种信息处理系统，例如主机计算机，其包括作为其一部分的壳体，其中具有包括电路化基板的电组件，该电组件又包括多个邻接的开放段，其限定导电层内的相对边缘部分，以隔离单独的 导电层的部分，使得该层可用于不同的功能，例如作为系统内的功率和接地元件。 至少一个电气部件位于系统的电气组件的电路化基板上并电耦合到电路基板。

公开(公告)号：US07491068B2

公开(公告)日：2009-02-17

申请号：US11865436

申请日：2007-10-01

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R12/00

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

Abstract translation: 包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入器。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触 飞机 还提供了一种制造焊盘栅格阵列中介层结构的方法。