公开(公告)号：US07827680B2

公开(公告)日：2010-11-09

申请号：US10751428

申请日：2004-01-06

Applicant: Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

Inventor： Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

IPC: H05K3/20

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An electroplating process of electroplating an electrically conductive substrate is described. The process includes electroplating intermittently to a predetermined plating thickness using the substrate surface as a cathode and a plating metal as an anode at a constant voltage between the anode and the cathode by repeating application of a voltage between a cathode and an anode and interruption of the application alternately. It is described that a voltage time/interruption time ratio is 0.1 to 1.0, a voltage time is not longer than 10 seconds, and an interruption time is not less than 1 x 10-12 seconds.

Abstract translation: 描述了对导电基板进行电镀的电镀工艺。 该工艺包括通过在阴极和阳极之间重复施加电压并使阴极和阳极之间的电压中断，在阳极和阴极之间以恒定电压将衬底表面作为阴极和电镀金属作为阳极间歇地电镀到预定的镀层厚度 交替应用。 描述了电压时间/中断时间比为0.1至1.0，电压时间不长于10秒，并且中断时间不小于1×10-12秒。

公开(公告)号：US20100243305A1

公开(公告)日：2010-09-30

申请号：US12732635

申请日：2010-03-26

Applicant: Ayao NIKI ,  Atsushi Ishida ,  Ryojiro Tominaga

Inventor： Ayao NIKI ,  Atsushi Ishida ,  Ryojiro Tominaga

IPC: H05K1/00 ,  C08F2/48 ,  B05D3/06

CPC classification number: H05K3/0032 ,  C25D5/02 ,  C25D7/12 ,  C25D7/123 ,  H05K3/387 ,  H05K3/422 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09581 ,  H05K2201/09827 ,  H05K2203/095 ,  H05K2203/1572 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for manufacturing a substrate with a metal film includes preparing an insulative substrate having the first surface and the second surface on the opposite side of the first surface, forming in the insulative substrate a penetrating hole having the inner wall tapering from the first surface of the insulative substrate toward the second surface, forming a layer of a composition containing a polymerization initiator and a polymerizable compound on the inner wall of the penetrating hole, irradiating the layer of the composition with energy such that a polymer is formed on the inner wall of the penetrating hole, applying a plating catalyst on the polymer, and forming a plated-metal film on the inner wall of the penetrating hole.

Abstract translation: 一种用金属膜制造衬底的方法包括制备在第一表面的相对侧具有第一表面和第二表面的绝缘衬底，在绝缘衬底中形成具有从第一表面的第一表面逐渐变细的内壁的穿透孔 所述绝缘基板朝向所述第二表面，在所述穿透孔的内壁上形成含有聚合引发剂和可聚合化合物的组合物层，用能量照射所述组合物层，使得聚合物形成在所述聚合物的内壁上 穿孔，在聚合物上涂布电镀催化剂，在贯通孔的内壁上形成电镀金属膜。

公开(公告)号：US07805689B2

公开(公告)日：2010-09-28

申请号：US11675304

申请日：2007-02-15

Applicant: Akira Ueda ,  Hideharu Matsushita

Inventor： Akira Ueda ,  Hideharu Matsushita

IPC: G06F17/50

CPC classification number: H05K3/0005 ,  G06F17/5018 ,  G06F17/5081 ,  G06F2217/16 ,  G06F2217/80 ,  H05K1/0201 ,  H05K1/115 ,  H05K2201/09536

Abstract: A circuit information acquisition and conversion device, a method, and a program therefor for acquiring a layer configuration, wire traces and shapes of via holes from circuit board design information; optimizing, before conversion into an analysis model, the output target range of the via holes on the basis of a package area, heat density distribution, and power consumption; and creating an analysis model that is suitable for a purpose of the analysis are provided.

Abstract translation: 一种用于从电路板设计信息获取层配置，线迹和通孔形状的电路信息获取和转换装置，方法和程序; 在转换成分析模型之前，根据封装面积，热密度分布和功耗来优化通孔的输出目标范围; 并提供了适用于分析目的的分析模型。

公开(公告)号：US07800216B2

公开(公告)日：2010-09-21

申请号：US10565078

申请日：2005-02-03

Applicant: Yasushi Inagaki ,  Katsuyuki Sano

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H01L23/14

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/056 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/09736 ,  H05K2201/098 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An IC chip for a high frequency region, particularly, a packaged substrate in which no malfunction or error occurs even if 3 GHz is exceeded. A conductive layer is formed at a thickness of 30 μm on a core substrate and a conductive circuit on an interlayer resin insulation layer is formed at a thickness of 15 μm. By thickening the conductive layer, the volume of the conductor itself can be increased thereby decreasing its resistance. Further, by using the conductive layer as a power source layer, the capacity of supply of power to an IC chip can be improved.

Abstract translation: 一种用于高频区域的IC芯片，特别是即使超过3GHz也不发生故障或错误的封装衬底。 在芯基板上形成厚度为30μm的导电层，在层间树脂绝缘层上形成厚度为15μm的导电电路。 通过增厚导电层，导体本身的体积可以增加，从而减小其电阻。 此外，通过使用导电层作为电源层，可以提高向IC芯片供电的能力。

公开(公告)号：US07795995B2

公开(公告)日：2010-09-14

申请号：US10590851

申请日：2005-02-23

Applicant: George E. White ,  Madhavan Swaminathan ,  Venkatesh Sundaram ,  Sidharth Dalmia

Inventor： George E. White ,  Madhavan Swaminathan ,  Venkatesh Sundaram ,  Sidharth Dalmia

IPC: H01P5/12 ,  H01P3/08

CPC classification number: H05K1/16 ,  H01L23/552 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P1/203 ,  H01P1/20381 ,  H01P1/2135 ,  H01P5/10 ,  H03H7/0115 ,  H03H7/075 ,  H03H7/09 ,  H03H7/1708 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/1775 ,  H03H7/38 ,  H03H7/42 ,  H03H7/463 ,  H03H2001/0085 ,  H05K1/024 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4644 ,  H05K3/4673 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/09536 ,  H01L2924/00

Abstract: The present invention provides all organic fully-packaged miniature bandpass filters, baluns, diplexers, multiplexers, couplers and a combination of the above manufactured using liquid crystalline polymer (LCP) and other multilayer polymer based substrates. These devices are manufactured using one or more LCP layers having integrated passive components formed thereon to provide the density and performance necessary for multi-band wireless devices. In the designs involving multiple LCP layers, the LCP layers are separated by prepeg layers. In accordance with an aspect of the present invention, coplanar waveguide, hybrid stripline/coplanar waveguide and/or microstrip topologies are utilized to form the integrated passive components, and the devices can be mass produced on large area panels at least 18 inches by 12 inches with line widths smaller than 10 um.

Abstract translation: 本发明提供了使用液晶聚合物（LCP）和其它多层聚合物基底板制造的所有有机全封装微型带通滤光器，平衡 - 不平衡转换器，双工器，多路复用器，耦合器和上述组合。 这些设备使用一个或多个LCP层制造，其中形成有集成的无源元件，以提供多频带无线设备所需的密度和性能。 在涉及多个LCP层的设计中，LCP层被预制层隔开。 根据本发明的一个方面，共面波导，混合带状线/共面波导和/或微带线拓扑被用于形成集成的无源部件，并且可以在大面积的面板上批量生产至少18英寸×12英寸 线宽小于10um。

公开(公告)号：US20100226108A1

公开(公告)日：2010-09-09

申请号：US12784634

申请日：2010-05-21

Applicant: Yasushi INAGAKI ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi INAGAKI ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/42

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed circuit board including a core substrate including a first resin substrate, a second resin substrate having an opening and a third resin substrate in a multilayer manner while interposing bonding plates, insulating layers and conductive circuit layers alternately laminated on the core substrate, solder bumps formed on an outer surface of the printed circuit board, a first capacitor formed in the opening of the second resin substrate, a conductive pad formed on the first resin substrate and connected to an electrode of the first capacitor, a via hole formed in the first resin substrate and directly connected to the conductive pad and a conductive circuit on the core substrate, and a second capacitor mounted on a surface of the printed circuit board.

Abstract translation: 一种印刷电路板，包括具有第一树脂基板的芯基板，具有开口的第二树脂基板和第三树脂基板，同时插入在芯基板上交替层叠的接合板，绝缘层和导电电路层，焊料凸块 形成在所述印刷电路板的外表面上的第一电容器，形成在所述第二树脂基板的开口中的第一电容器，形成在所述第一树脂基板上并连接到所述第一电容器的电极的导电焊盘， 树脂基板，并且直接连接到导电焊盘和芯基板上的导电电路，以及安装在印刷电路板的表面上的第二电容器。

公开(公告)号：US20100218891A1

公开(公告)日：2010-09-02

申请号：US12776771

申请日：2010-05-10

Applicant: Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

Inventor： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

IPC: C09J5/06

CPC classification number: H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4641 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1092

Abstract: A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

Abstract translation: 多层互连结构和形成方法。 在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。 在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。

公开(公告)号：US07781681B2

公开(公告)日：2010-08-24

申请号：US12163286

申请日：2008-06-27

Applicant: Takashi Kariya

Inventor： Takashi Kariya

IPC: H05K1/16

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/113 ,  H05K1/115 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10674 ,  Y10T29/49139

Abstract: A multilayer printed wiring board includes a core substrate and a built-up wiring layer formed by alternately layering conductor circuits and insulating resin layers. The built-up wiring layer includes a first surface provided in contact with the core substrate and a second surface opposing the first surface and including a mounting area on which at least one semiconductor device is to be mounted. A first plurality of through-hole conductors is formed in a first portion of the core substrate which corresponds to the mounting area of the second surface, and a second plurality of through-hole conductors formed in a second portion of the core substrate which corresponds to another area of the second surface other than the mounting area. A pitch between the first plurality of through-hole conductors is smaller than a pitch between the second plurality of through-hole conductors. In one aspect, a ratio of pads to through holes directly below a processor core section of the semiconductor device is less that a number of pads to through holes in an area outside the processor core.

Abstract translation: 多层印刷电路板包括芯基板和通过交替层叠导体电路和绝缘树脂层而形成的积层布线层。 所述积层布线层包括与所述芯基板接触的第一表面和与所述第一表面相对的第二表面，并且包括将要安装至少一个半导体器件的安装区域。 第一多个通孔导体形成在芯基板的与第二表面的安装面积对应的第一部分中，第二多个通孔导体形成在芯基板的第二部分中，其对应于 第二表面的另一区域，而不是安装区域。 第一多个通孔导体之间的间距小于第二多个通孔导体之间的节距。 在一个方面，焊盘与半导体器件的处理器核心部分正下方的通孔的比例小于处理器核心外部区域中通孔的数量。

公开(公告)号：US07748115B2

公开(公告)日：2010-07-06

申请号：US11777988

申请日：2007-07-13

Applicant: Sunappan Vasudivan ,  Chee Wai Lu ,  Boon Keng Lok

Inventor： Sunappan Vasudivan ,  Chee Wai Lu ,  Boon Keng Lok

IPC: H01K3/10 ,  H05K7/00

CPC classification number: H05K1/186 ,  H05K1/0231 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A method of forming a circuit board, the method comprising mounting at least one passive component on a first surface of a first laminate material; interconnecting the passive component to contact traces and vias of the first laminate material; and attaching a second laminate material to the first surface of the first laminate material utilizing a lamination process, the second laminate material sheet having at least one of a recess, a through-hole or both formed therein for accommodating the passive component in the second laminate.

Abstract translation: 一种形成电路板的方法，所述方法包括在第一层压材料的第一表面上安装至少一个无源部件; 将所述被动部件与所述第一层压材料的接触迹线和通孔相互连接; 并且利用层压工艺将第二层压材料附着到第一层压材料的第一表面上，第二层压材料板具有形成在其中的凹部，通孔或两者中的至少一个，用于容纳第二层压体中的被动部件 。

公开(公告)号：US07745737B2

公开(公告)日：2010-06-29

申请号：US11478922

申请日：2006-06-30

Applicant: Yu-Hsu Lin ,  Shang-Tsang Yeh ,  Chao-Chen Huang ,  Chuan-Bing Li

Inventor： Yu-Hsu Lin ,  Shang-Tsang Yeh ,  Chao-Chen Huang ,  Chuan-Bing Li

IPC: H01R12/04 ,  H05K1/11 ,  H01K3/22

CPC classification number: H05K1/116 ,  H05K1/0216 ,  H05K3/429 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09718 ,  Y10T29/49165

Abstract: A printed circuit board (PCB) having vias for reducing reflections of input signals includes a first signal layer, a second signal layer, one via, an input signal line arranged on the first signal layer, and an output signal line arranged on the second signal layer. The via further includes a drill hole, a first pad, and a second pad. The first pad is electrically connected with the input signal line, and the second pad is electrically connected with the output signal line. An outer diameter of the first pad is smaller than an outer diameter of the second pad.

Abstract translation: 具有用于减少输入信号的反射的通孔的印刷电路板（PCB）包括第一信号层，第二信号层，一个通孔，布置在第一信号层上的输入信号线和布置在第二信号上的输出信号线 层。 通孔还包括钻孔，第一垫和第二垫。 第一焊盘与输入信号线电连接，第二焊盘与输出信号线电连接。 第一垫的外径小于第二垫的外径。