公开(公告)号：US20040211594A1

公开(公告)日：2004-10-28

申请号：US10737412

申请日：2003-12-15

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H05K001/11 ,  H05K003/42

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K3/3468 ,  H05K3/4007 ,  H05K3/4069 ,  H05K3/429 ,  H05K2201/0367 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2201/10666 ,  Y02P70/613 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A vertical routing structure for a multi-layered substrate having a lamination structure therein. The lamination structure has at least a through hole that links up both surfaces of the lamination structure. The vertical routing structure comprises a conductive rod and a conductive layer. The conductive rod is formed inside the through-hole with the ends protruding above the respective upper and lower surface of the lamination structure. The conductive layer is positioned in the space between the interior sidewall of the through-hole and the conductive rod. The vertical routing structure on the substrate is able to reduce the area for laying the required circuits or increase the wiring density in a given area.

Abstract translation: 一种用于其中具有层压结构的多层基板的垂直布线结构。 层压结构至少具有连接层压结构的两个表面的通孔。 垂直布线结构包括导电棒和导电层。 导电杆形成在通孔的内部，端部突出在层叠结构的相应的上表面和下表面的上方。 导电层位于通孔的内侧壁与导电棒之间的空间中。 基板上的垂直布线结构能够减少放置所需电路的面积或增加给定区域中的布线密度。

公开(公告)号：US06801174B2

公开(公告)日：2004-10-05

申请号：US10005960

申请日：2001-12-03

Applicant: Shun Kayama ,  Shunji Amano ,  Motosuke Ohmi ,  Junichi Ohsako ,  Ryota Odake ,  Hiroshi Ozaki

Inventor： Shun Kayama ,  Shunji Amano ,  Motosuke Ohmi ,  Junichi Ohsako ,  Ryota Odake ,  Hiroshi Ozaki

IPC: H01J162

CPC classification number: H05K3/363 ,  H01L27/32 ,  H05K3/305 ,  H05K3/3489 ,  H05K2201/09481 ,  H05K2201/09572 ,  H05K2201/10128 ,  H05K2201/10666 ,  H05K2203/041 ,  H05K2203/107

Abstract: A display device includes an organic electrroluminescence device provided on a first substrate, conductive metallic films provided on the first substrate at such positions as not to overlap with the organic electroluminescence device, a second substrate having a plurality of holes and conductive connection portions which are provided at peripheral portions forming the holes, and solder portions charged in the holes of the second substrate and, by being melted, electrically connecting the conductive metallic films of the first substrate with the conductive connection portions of the second substrate.

Abstract translation: 显示装置包括设置在第一基板上的有机电致发光器件，设置在不与有机电致发光器件重叠的位置处的第一基板上的导电金属膜，具有多个孔的第二基板和设置有导电连接部的导电连接部 在形成孔的周边部分，以及填充在第二基板的孔中的焊料部分，并且通过熔化将第一基板的导电金属膜与第二基板的导电连接部分电连接。

公开(公告)号：US20040016114A1

公开(公告)日：2004-01-29

申请号：US10202726

申请日：2002-07-25

Applicant: International Business Machines Corporation

Inventor： Michael F. McAllister ,  John G. Torok

IPC: H05K003/20 ,  H05K001/00

CPC classification number: H05K1/141 ,  H05K1/0286 ,  H05K1/162 ,  H05K3/325 ,  H05K3/3436 ,  H05K3/429 ,  H05K2201/049 ,  H05K2201/09309 ,  H05K2201/10348 ,  H05K2201/10666 ,  H05K2201/10719 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49169

Abstract: A Land Grid Array structure is enhanced with a flex film interposer that not only provides a Land Grid Array (LGA) electrical connection between a Multi-Chip Module (MCM) and the next level of integration such as a system board, but also provides a reliable means to implement desired Engineering Change (EC) capability as well as a means for decoupling power to ground structure to minimize switching activity effects on the System. The invention as described can be implemented for EC repair, for Capacitive Decoupling or both.

公开(公告)号：US06560121B1

公开(公告)日：2003-05-06

申请号：US09554595

申请日：2000-05-26

Applicant: Jean-Yves Daden ,  Muriel Gohn-Devineau ,  Gérard Cachier ,  Pascal Etourneau ,  Vincent Jahier ,  Alain Grancher ,  Ludovic Michel

Inventor： Jean-Yves Daden ,  Muriel Gohn-Devineau ,  Gérard Cachier ,  Pascal Etourneau ,  Vincent Jahier ,  Alain Grancher ,  Ludovic Michel

IPC: H05K702

CPC classification number: H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6644 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/12041 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/0243 ,  H05K3/0061 ,  H05K3/3442 ,  H05K2201/09054 ,  H05K2201/09072 ,  H05K2201/09745 ,  H05K2201/10666 ,  H05K2201/10727 ,  H05K2203/0455 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: The surface mounting of a backset microwave package on a printed circuit. After the package has been accurately positioned against the printed circuit the connections are produced by soldering the conducting elements in direct contact. A chip is enclosed in a sort of cage constituting a screen which replaces a conventional cover, the cage is formed by layouts borne respectively by the package and the printed circuit and is linked together by metal links. The surface mounting is particularly applicable to packages operating in millimetric microwaves.

Abstract translation: 背板微波封装在印刷电路上的表面安装。 在封装已经精确地定位在印刷电路上之后，通过直接接触导电元件来焊接连接。 芯片被封装在构成屏幕的笼子中，其替代传统的盖子，保持架由分别由包装和印刷电路承载的布局形成，并通过金属连接件连接在一起。 表面安装特别适用于以毫米微波工作的封装。

公开(公告)号：US06468834B1

公开(公告)日：2002-10-22

申请号：US09452851

申请日：1999-12-02

Applicant: Ahmad Hamzehdoost

Inventor： Ahmad Hamzehdoost

IPC: H01L2148

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/4046 ,  H05K2201/0305 ,  H05K2201/10666 ,  Y02P70/613 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A die-up configuration includes a rigid circuit board with electrically conductive plated-through holes formed therethrough and an integrated-circuit die mounted to the upper surface of which a flexible insulated tape layer is fixed to the upper surface of a rigid circuit board and which has a number of wire-bonding sites. Conductive vias or plated-through holes are provided for connecting the wire-bonding sites on the upper surface of the flexible insulated tape layer to the contact areas formed on the lower surface of the flexible insulated tape layer. Conductors are provided for connecting respective contact areas on the lower surface of the flexible insulated tape layer to solder balls on the bottom of the rigid circuit board.

Abstract translation: 裸芯片配置包括刚性电路板，其具有穿过其中形成的导电电镀通孔，以及安装到其上表面的集成电路裸片，柔性绝缘带层固定到刚性电路板的上表面， 具有多个引线接合点。 提供导电通孔或电镀通孔，用于将柔性绝缘带层的上表面上的引线接合位置与形成在柔性绝缘带层的下表面上的接触区域相连接。 提供导体，用于将柔性绝缘带层的下表面上的各个接触区域连接到刚性电路板底部的焊球。

公开(公告)号：US06444924B1

公开(公告)日：2002-09-03

申请号：US09359981

申请日：1999-07-23

Applicant: Naoto Ishida ,  Kouji Asano

Inventor： Naoto Ishida ,  Kouji Asano

IPC: H01R109

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12033 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H05K3/308 ,  H05K3/3426 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09481 ,  H05K2201/10234 ,  H05K2201/10318 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2201/10871 ,  Y02P70/613 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A printed wiring board has a circuit substrate 6 having a conductor circuit 5 and a through hole 60, and also has a joining pin 1 inserted into the through hole. The joining pin is manufactured by using a material unmelted at a heating temperature in joining the joining pin to an opposite party pad 81. The joining pin is constructed by a joining head portion 11 having a greater diameter than an opening diameter of the through hole. The joining pin forms a joining portion for joining and connection to the opposite party pad. The joining pin has a leg portion 12 having a diameter smaller than the through hole. The leg portion is inserted into the through hole and is joined to the through hole by a conductive material such as a soldering material 20, etc. In lieu of a joining pin, a joining ball approximately having a spherical shape can be joined to the through hole by the conductive material.

Abstract translation: 印刷电路板具有电路基板6，电路基板6具有导体电路5和通孔60，并且还具有插入到通孔中的接合销1。 接合销通过使用在加热温度下未熔化的材料来制造，该材料将接合销接合到相对方垫81.接合销由具有比通孔的开口直径更大的直径的接合头部11构成。 接合销形成用于接合和连接到对方垫的接合部分。 连接销具有直径比通孔小的腿部12。 腿部插入到通孔中，并且通过诸如焊接材料20等的导电材料接合到通孔。代替接合销，可以将大致具有球形的接合球接合到通孔 孔由导电材料制成。

公开(公告)号：US20020056897A1

公开(公告)日：2002-05-16

申请号：US10033397

申请日：2001-12-27

Inventor： Hiromi Yatsuda

IPC: H01L023/02

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L24/97 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/10666 ,  H05K2203/1147 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: A first substrate has a plurality of bumps and a second substrate has a plurality of openings at positions in registration with the plurality of bumps when the first and second substrates are placed one on top of the other in a confronting manner. The first and second substrates are put together by fusing a sealing wall formed on the second substrate, to hermetically seal an electronic device lying on the first substrate therein. Gas that may be generated upon fusing of the sealing wall can be effectively removed through the openings in the second substrate.

Abstract translation: 第一基板具有多个凸块，并且当第一和第二基板以相对的方式一个放置在另一个基板上时，第二基板在与多个凸块对准的位置处具有多个开口。 通过将形成在第二基板上的密封壁融合，将第一和第二基板放置在一起，将位于其上的第一基板上的电子设备密封。 可以通过第二基板中的开口有效地去除在密封壁融合时产生的气体。

公开(公告)号：US06344609B1

公开(公告)日：2002-02-05

申请号：US09586659

申请日：2000-06-01

Applicant: Kazuhiro Nakano

Inventor： Kazuhiro Nakano

IPC: H05K900

CPC classification number: H01L23/49805 ,  H01L2224/32225 ,  H05K1/0243 ,  H05K3/3442 ,  H05K2201/09181 ,  H05K2201/09381 ,  H05K2201/10075 ,  H05K2201/10666 ,  H05K2201/10727 ,  Y02P70/613

Abstract: An electronic unit is provided that effectively utilizes the upper surface of a circuit board as a wiring pattern and reduces the size of the electronic unit. Wiring patterns and grounding patterns are provided on the upper surface of a circuit board. The wiring patterns and grounding patterns are connected to wiring terminal electrode portions and grounding terminal electrode portions by connection conductors, respectively, provided in through-holes. This allows a cover, covering electronic parts on the circuit board, to be effectively mounted as the entire outer periphery of the first surface of the circuit board is covered.

Abstract translation: 提供一种电子单元，其有效地利用电路板的上表面作为布线图案并且减小电子单元的尺寸。 在电路板的上表面上提供接线图案和接地图案。 布线图案和接地图案分别通过设置在通孔中的连接导体连接到布线端子电极部分和接地端子电极部分。 由此，覆盖电路基板的第一面的整个外周的情况下，能够有效地安装覆盖电路基板上的电子部件的盖。

公开(公告)号：US20010034937A1

公开(公告)日：2001-11-01

申请号：US09859690

申请日：2001-05-17

Applicant: International Business Machines Corporation

Inventor： Bernd K. Appelt ,  Saswati Datta ,  Michael A. Gaynes ,  John M. Lauffer ,  James R. Wilcox

IPC: H05K003/36 ,  H01R043/00

CPC classification number: H05K3/325 ,  H05K3/4614 ,  H05K2201/0373 ,  H05K2201/09536 ,  H05K2201/10666 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49165 ,  Y10T29/49194

Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a nullthrough via.null

公开(公告)号：US20010030062A1

公开(公告)日：2001-10-18

申请号：US09782384

申请日：2001-02-12

Inventor： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

IPC: H05K001/11 ,  H01R012/04 ,  B32B015/00 ,  B32B017/06 ,  H01B001/00 ,  H01C001/00

CPC classification number: H05K3/363 ,  H01L23/49883 ,  H01L2224/16503 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10666 ,  H05K2203/0425 ,  H05K2203/0455

Abstract: A conductive composition, and articles and methods using the conductive composition are disclosed.

Abstract translation: 公开了一种导电组合物，以及使用该导电组合物的制品和方法