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公开(公告)号：US11797222B2
公开(公告)日：2023-10-24
申请号：US17577012
申请日：2022-01-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Po-Cheng Su , Chih-Wei Wang , Wei Lin
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.
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82.发明公开公开(公告)号：US20230214150A1
公开(公告)日：2023-07-06
申请号：US17679109
申请日：2022-02-24
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Chun-Wei Tsao , Hsiao-Yi Lin , Wei Lin
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.
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公开(公告)号：US20230071724A1
公开(公告)日：2023-03-09
申请号：US17498771
申请日：2021-10-12
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jia-Fan Chien , Wei Lin , Yu-Cheng Hsu , Yu-Siang Yang
Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: detecting a first temperature status of a rewritable non-volatile memory module; performing a first write operation on a first physical unit under the first temperature status to store first data to the first physical unit; after performing the first write operation, detecting a second temperature status of the rewritable non-volatile memory module; in response to the first temperature status and the second temperature status meeting a first condition, performing a data refresh operation on the first physical unit under the second temperature status to re-store the first data to a second physical unit different from the first physical unit.
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公开(公告)号：US20220342547A1
公开(公告)日：2022-10-27
申请号：US17349918
申请日：2021-06-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Siang Yang , Yu-Cheng Hsu , Tsai-Hao Kuo , Wei Lin , An-Cheng Liu
IPC: G06F3/06
Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.
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公开(公告)号：US20220334723A1
公开(公告)日：2022-10-20
申请号：US17242240
申请日：2021-04-27
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Siang Yang , Wei Lin , An-Cheng Liu , Yu-Heng Liu , Chun-Hsi Lai , Ting-Chien Zhan
IPC: G06F3/06
Abstract: A flash memory control method, a flash memory storage device and a flash memory controller are provided. The method includes the following. A flash memory module is instructed to perform a data merge operation to copy first data in a first physical unit into at least one second physical unit. After the first data is copied and before the first physical unit is erased, another programming operation is performed on the first physical unit to change a data storage state of at least a part of memory cells in the first physical unit from a first state into a second state. After the first physical unit is programmed, an erase operation is performed on the first physical unit.
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Patent Agency Ranking
公开(公告)号：US10984870B2
公开(公告)日：2021-04-20
申请号：US16292338
申请日：2019-03-05
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , An-Cheng Liu , Szu-Wei Chen , Yu-Siang Yang
IPC: G11C16/12 , G11C11/4091 , G11C16/34 , G11C16/26
Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading a first physical unit based on a first read voltage level to obtain first data; reading the first physical unit based on a second read voltage level to obtain second data; reading the first physical unit based on a third read voltage level to obtain third data; obtaining a first reference value which reflects a data variation status between the first data and the second data; obtaining a second reference value which reflects a data variation status between the first data and the third data; reading the first physical unit based on a fourth read voltage level to obtain fourth data according to the first reference value and the second reference value; and decoding the fourth data by a decoding circuit.
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公开(公告)号：US10892026B2
公开(公告)日：2021-01-12
申请号：US16003114
申请日：2018-06-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , An-Cheng Liu , Szu-Wei Chen , Yu-Siang Yang
Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: programming first data into a plurality of first memory cells in the rewritable non-volatile memory module, such that the programmed first memory cells have a plurality of states; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.
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公开(公告)号：US20200227120A1
公开(公告)日：2020-07-16
申请号：US16292338
申请日：2019-03-05
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , An-Cheng Liu , Szu-Wei Chen , Yu-Siang Yang
IPC: G11C16/12 , G11C16/26 , G11C16/34 , G11C11/4091
Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading a first physical unit based on a first read voltage level to obtain first data; reading the first physical unit based on a second read voltage level to obtain second data; reading the first physical unit based on a third read voltage level to obtain third data; obtaining a first reference value which reflects a data variation status between the first data and the second data; obtaining a second reference value which reflects a data variation status between the first data and the third data; reading the first physical unit based on a fourth read voltage level to obtain fourth data according to the first reference value and the second reference value; and decoding the fourth data by a decoding circuit.
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公开(公告)号：US10679707B2
公开(公告)日：2020-06-09
申请号：US16120313
申请日：2018-09-03
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Tsai-Hao Kuo , Szu-Wei Chen , Lih Yuarn Ou , Hsiao-Yi Lin
Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.
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公开(公告)号：US10586596B2
公开(公告)日：2020-03-10
申请号：US15412065
申请日：2017-01-23
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Szu-Wei Chen
Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units and a memory control circuit unit and a memory storage apparatus using the same are provided. Each of the physical erasing units has a plurality of physical programming unit sets, and each of the physical programming unit sets has a plurality of physical programming unit. The method includes receiving data and arranging the data to generate a first data stream and a second data stream. The method also includes encoding the first data stream and the second data stream to generate a third data stream, and issuing a programming command sequence to write the first data stream, the second data stream and the third data stream respectively into a first physical programming unit, a second physical programming unit and a third physical programming unit of a physical programming unit set.
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