公开(公告)号：US20150173178A1

公开(公告)日：2015-06-18

申请号：US14104186

申请日：2013-12-12

Applicant: ECHOSTAR TECHNOLOGIES L.L.C.

Inventor： Adam Charles Morzos

IPC: H05K1/02 ,  H05K3/34 ,  H05K1/18

CPC classification number: H05K3/3452 ,  H05K1/0201 ,  H05K1/0269 ,  H05K2201/0166 ,  H05K2203/0571 ,  H05K2203/161

Abstract: An electronic device is disclosed herein. In accordance with certain implementations, the electronic device includes a printed circuit board having electrically conductive traces formed thereon. The electronic device also includes a thermochromic solder mask layer overlying the electrically conductive traces. The thermochromic solder mask layer changes color in response to temperature changes associated with operation of the electronic device. The thermochromic characteristics of the solder mask layer are useful for purposes of indicating overheating of the electronic device, the conductive traces, or a region of the printed circuit board.

Abstract translation: 本文公开了一种电子设备。 根据某些实施方案，电子设备包括其上形成有导电迹线的印刷电路板。 电子器件还包括覆盖导电迹线的热致变色焊料掩模层。 热变色阻焊层响应于与电子设备的操作相关的温度变化而改变颜色。 焊接掩模层的热致变色特征可用于指示电子器件，导电迹线或印刷电路板的区域的过热。

公开(公告)号：US20150125674A1

公开(公告)日：2015-05-07

申请号：US14071879

申请日：2013-11-05

Applicant: Thomas B. Brust ,  Mark Edward Irving ,  Catherine A. Falkner ,  Anne Troxell Wyand

Inventor： Thomas B. Brust ,  Mark Edward Irving ,  Catherine A. Falkner ,  Anne Troxell Wyand

IPC: G03F7/40 ,  G03F7/20 ,  G03F7/039 ,  G03F7/16

CPC classification number: G03F7/40 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/1641 ,  C23C18/204 ,  C23C18/208 ,  C23C18/30 ,  C23C18/38 ,  G03F7/039 ,  G03F7/16 ,  G03F7/20 ,  H05K3/185 ,  H05K2201/0166 ,  H05K2201/0236 ,  H05K2203/0759 ,  Y10T428/24917

Abstract: A conductive pattern is prepared in a polymeric layer that has (a) a reactive polymer comprising pendant tertiary alkyl ester groups, (b) a compound that provides an acid upon exposure to radiation having a λmax of at least 150 nm and up to and including 450 nm, and (c) a crosslinking agent. The polymeric layer is patternwise exposed to provide a polymeric layer comprising non-exposed regions and exposed regions comprising a polymer comprising carboxylic acid groups. The exposed regions are contacted with electroless seed metal ions to form a pattern of electroless seed metal ions. The pattern of electroless seed metal ions is then reduced to provide a pattern of corresponding electroless seed metal nuclei. The corresponding electroless seed metal nuclei are then electrolessly plated with a conductive metal.

Abstract translation: 在聚合物层中制备导电图案，该聚合物层具有（a）包含叔烷基酯基侧基的反应性聚合物，（b）在暴露于λmax为至少150nm并且包括 450nm，（c）交联剂。 图案化地暴露聚合物层以提供包含非暴露区域的聚合物层和包含包含羧酸基团的聚合物的暴露区域。 暴露的区域与无电子种子金属离子接触以形成无电子种子金属离子的图案。 然后减少无电子种子金属离子的图案以提供相应的无电子种子金属核的图案。 然后将相应的无电子种子金属核用导电金属无电镀。

公开(公告)号：US08258411B2

公开(公告)日：2012-09-04

申请号：US12548933

申请日：2009-08-27

Applicant: Alan E. Wang ,  Kevin C. Olson

Inventor： Alan E. Wang ,  Kevin C. Olson

IPC: H05K1/11

CPC classification number: H05K3/445 ,  H01L2224/16225 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/426 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0129 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/09154 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2201/09645 ,  H05K2201/09827 ,  H05K2203/1105 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board includes an electrically conductive sheet having an insulative coating surrounding the conductive sheet, with a surface of the insulative coating around an edge of the conductive sheet having an arcuate or rounded shape. At least one electrical conductor is conformally deposited on at least the rounded insulative coating around the edge of the conductive sheet and defined via photolithographic and metallization techniques. Each electrical conductor on the insulative coating thereon around the edge of the conductive sheet conforms to the arcuate or rounded shape of the insulative coating and, therefore, has an arcuate or rounded shape.

Abstract translation: 电路板包括具有围绕导电片的绝缘涂层的导电片，绝缘涂层的表面围绕导电片的边缘具有弓形或圆形形状。 至少一个电导体被共形沉积在导电片的边缘周围的至少圆形绝缘涂层上，并通过光刻和金属化技术限定。 导电片边缘周围的绝缘涂层上的每个电导体符合绝缘涂层的弧形或圆形形状，因此具有弓形或圆形形状。

公开(公告)号：US08105690B2

公开(公告)日：2012-01-31

申请号：US10775174

申请日：2004-02-11

Applicant: Ernest L. Lawton ,  Robert B. Rau ,  Garry D. Puckett

Inventor： Ernest L. Lawton ,  Robert B. Rau ,  Garry D. Puckett

IPC: D02G3/00 ,  B32B9/00

CPC classification number: D02G3/00 ,  C03C25/00 ,  C03C25/10 ,  C03C25/26 ,  C03C25/323 ,  C03C25/36 ,  C03C25/47 ,  C03C25/48 ,  C08J5/08 ,  H05K1/0366 ,  H05K2201/0166 ,  H05K2201/0175 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0245 ,  H05K2203/127 ,  Y10T428/2927 ,  Y10T428/2933 ,  Y10T428/2938 ,  Y10T428/2962 ,  Y10T428/2964

Abstract: The present invention provides a glass fiber product having particles adhered to at least one fiber of the product, where the size and amount of particles is effective to reduce the tackiness of the glass fiber product and optionally effective to reduce interfilament bonding, and composition, and method for forming the same.

Abstract translation: 本发明提供了一种玻璃纤维产品，其具有附着到产品的至少一种纤维上的颗粒，其中颗粒的尺寸和数量有效地降低玻璃纤维产品的粘性，并且可选地有效地减少纤维间粘合，以及组合物，和 其形成方法。

公开(公告)号：US07992290B2

公开(公告)日：2011-08-09

申请号：US11940900

申请日：2007-11-15

Applicant: Ying-Lin Chen ,  Yung-Chou Chen

Inventor： Ying-Lin Chen ,  Yung-Chou Chen

IPC: H05K3/36 ,  B32B3/10

CPC classification number: H05K3/427 ,  H05K1/0393 ,  H05K1/181 ,  H05K3/4652 ,  H05K2201/0166 ,  H05K2201/043 ,  H05K2201/09536 ,  H05K2203/0264 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T156/1052 ,  Y10T428/24273

Abstract: An exemplary method of making an FPC includes forming a substrate comprising metal foil layers interleaved with intervening layers by: (a) laminating intervening layers with metal foil layers; (b) adhering a covering film to outermost surfaces of the substrate; (c) defining a hole in one side of the substrate through the covering film and at least two metal foil layers and the intervening layer between the at least two metal foil layers by etching or laser technology; and (d) plating a portion of an inner wall of the hole with conductive material to form a via to electrically connect the at least two metal foil layers.

Abstract translation: 制造FPC的示例性方法包括：通过以下步骤形成包含与中间层交错的金属箔层的基板：（a）将介入层与金属箔层层压; （b）将覆盖膜粘附到基板的最外表面; （c）通过蚀刻或激光技术通过覆盖膜和至少两个金属箔层和至少两个金属箔层之间的中间层来限定衬底的一侧中的孔; 以及（d）用导电材料电镀所述孔的内壁的一部分以形成通孔以电连接所述至少两个金属箔层。

公开(公告)号：US20110062563A1

公开(公告)日：2011-03-17

申请号：US12560727

申请日：2009-09-16

Applicant: Xiaoyu Yang ,  Qing Li ,  Albert Meeks ,  Kim Le

Inventor： Xiaoyu Yang ,  Qing Li ,  Albert Meeks ,  Kim Le

IPC: H01L23/495 ,  H01L21/44 ,  H01L23/52

CPC classification number: H05K3/28 ,  G11C16/0483 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/83191 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/24 ,  H05K3/284 ,  H05K3/305 ,  H05K3/328 ,  H05K3/3452 ,  H05K2201/0166 ,  H05K2201/0769 ,  H05K2201/10159 ,  H05K2201/10575 ,  H05K2203/049 ,  H05K2203/1316 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Mobile ion diffusion causes a shift in the threshold voltage of non-volatile storage elements in a memory chip, such as during an assembly process of the memory chip. To reduce or avoid such shifts, a coating can be applied to a printed circuit board substrate or a leader frame to which the memory chip is surface mounted. An acrylic resin coating having a thickness of about 10 μm may be used. A memory chip is attached to the coating using an adhesive film. Stacked chips may be used as well. Another approach provides metal barrier traces over copper traces of the printed circuit board, within a solder mask layer. The metal barrier traces are fabricated in the same pattern as the copper traces but are wider so that they at least partially envelop and surround the copper traces. Corresponding apparatuses and fabrication processes are provided.

Abstract translation: 移动离子扩散导致存储芯片中的非易失性存储元件的阈值电压的偏移，例如在存储器芯片的组装过程中。 为了减少或避免这种偏移，可以将涂层施加到印刷电路板基板或表面安装存储芯片的引导框架。 可以使用厚度约为10μm的丙烯酸树脂涂层。 使用粘合膜将记忆芯片附着到涂层上。 也可以使用堆叠的芯片。 另一种方法在焊接掩模层内提供印刷电路板的铜迹线上的金属阻挡迹线。 金属阻挡迹线以与铜迹线相同的图案制造，但是更宽，使得它们至少部分地包围和包围铜迹线。 提供相应的装置和制造工艺。

公开(公告)号：US20100208440A1

公开(公告)日：2010-08-19

申请号：US12771501

申请日：2010-04-30

Applicant: Joel S. Peiffer ,  Nelson B. O'Bryan

Inventor： Joel S. Peiffer ,  Nelson B. O'Bryan

IPC: H05K1/18 ,  H01C1/012 ,  H01C17/00

CPC classification number: H05K1/162 ,  H05K1/095 ,  H05K1/16 ,  H05K1/167 ,  H05K3/429 ,  H05K2201/0166 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: A passive electrical article includes a first electrically conductive substrate having a major surface and a second electrically conductive substrate having a major surface. The major surface of the second substrate faces the major surface of the first substrate. An electrically resistive layer is on at least one of the major surface of the first substrate and the major surface of the second substrate. An electrically insulative layer is between the first and second substrates and in contact with the electrically resistive layer. The insulative layer is a polymer having a thickness ranging from about 1 μm to about 20 μm. The insulative layer has a substantially constant thickness.

Abstract translation: 无源电器件包括具有主表面的第一导电衬底和具有主表面的第二导电衬底。 第二基板的主表面面向第一基板的主表面。 电阻层位于第一基板的主表面和第二基板的主表面中的至少一个上。 电绝缘层位于第一和第二基板之间并与电阻层接触。 绝缘层是厚度为约1μm至约20μm的聚合物。 绝缘层具有基本恒定的厚度。

公开(公告)号：US20100065960A1

公开(公告)日：2010-03-18

申请号：US12557882

申请日：2009-09-11

Applicant: Katsuyoshi MINO ,  Masaru Kanakubo ,  Masami Motegi

Inventor： Katsuyoshi MINO ,  Masaru Kanakubo ,  Masami Motegi

IPC: H01L23/48 ,  H01L21/78 ,  H01L21/56 ,  H01L21/50

CPC classification number: H01L23/49531 ,  H01L21/565 ,  H01L23/49551 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/0554 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/056 ,  H05K3/284 ,  H05K2201/0166 ,  H05K2203/1316 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Provided is a circuit device manufacturing method for coating a bottom surface of a circuit board with a thin coating of sealing resin. In the present invention, a circuit board having a circuit element such as a semiconductor element embedded therein is placed in a molding die, and a resin sheet containing a thermosetting resin is interposed between the circuit board and a bottom surface of an inner wall of the molding die. Under this condition, the molding die is heated to about 180° C., and a sealing resin in liquid form is injected through a gate. Thereby, the bottom surface of the circuit board can be coated with a thin coating of the sealing resin made of the molten resin sheet.

Abstract translation: 提供了一种用薄型密封树脂涂覆电路板底面的电路器件制造方法。 在本发明中，将具有嵌入其中的半导体元件等电路元件的电路基板放置在成型模具中，将含有热固化性树脂的树脂片插入在电路基板与内部的内壁的底面之间 成型模具。 在这种条件下，将模具加热至约180℃，并通过浇口注入液体形式的密封树脂。 由此，电路板的底面可以涂覆有由熔融树脂片制成的密封树脂的薄涂层。

公开(公告)号：US07603769B2

公开(公告)日：2009-10-20

申请号：US11901162

申请日：2007-09-14

Applicant: My Jang

Inventor： My Jang

IPC: H05K3/30

CPC classification number: H05K3/3442 ,  H05K3/303 ,  H05K2201/0166 ,  H05K2201/09472 ,  H05K2201/10393 ,  H05K2201/10636 ,  H05K2201/2018 ,  H05K2203/0169 ,  H05K2203/0594 ,  H05K2203/0769 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T29/49171

Abstract: Methods of coupling a surface mount device with a substrate such as a printed circuit, for example, are disclosed. A method, according to one aspect, may include coupling a holder with a substrate such that terminals of the substrate are included in an opening of the holder, mounting an electronic device over the terminals with a conductive bonding material disposed there between, heating the conductive bonding material to its melting point, and cooling the conductive bonding material.

Abstract translation: 公开了将表面安装器件与印刷电路等基板连接的方法。 根据一个方面的一种方法可以包括将保持器与衬底连接，使得衬底的端子包括在保持器的开口中，将电子器件安装在端子之间，其中设置有导电接合材料，加热导电 将材料接合到其熔点，并冷却导电接合材料。

公开(公告)号：US20080314628A1

公开(公告)日：2008-12-25

申请号：US12021698

申请日：2008-01-29

Applicant: Ki Yong SONG ,  Sung-Hen CHO ,  Jun Hyuk MOON ,  Chang Oh JEONG ,  Hong Long NING

Inventor： Ki Yong SONG ,  Sung-Hen CHO ,  Jun Hyuk MOON ,  Chang Oh JEONG ,  Hong Long NING

IPC: H05K1/09 ,  B05D5/12

CPC classification number: H01L27/1288 ,  G02F1/136286 ,  G02F2001/136295 ,  G02F2202/42 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H05K3/002 ,  H05K3/0041 ,  H05K3/048 ,  H05K3/107 ,  H05K3/184 ,  H05K3/388 ,  H05K2201/0166 ,  H05K2203/0565

Abstract: Disclosed is a method of forming a metal pattern, the method comprising depositing a dielectric substrate on a supporting substrate; forming a latent mask pattern of a metal pattern on the dielectric substrate; etching the dielectric substrate exposed by the latent mask pattern; forming a seed layer on the supporting substrate by activating the supporting substrate; removing the latent mask pattern and the portion of the seed layer disposed on the latent mask pattern through a lift-off process; and plating a metal layer on the patterned seed layer.

Abstract translation: 公开了一种形成金属图案的方法，所述方法包括在支撑衬底上沉积电介质衬底; 在所述电介质基板上形成金属图案的潜像图案; 蚀刻由潜像图案曝光的电介质基片; 通过激活支撑衬底在支撑衬底上形成种子层; 通过剥离过程去除潜在掩模图案和设置在潜像图案上的种子层的部分; 并且在图案化种子层上镀覆金属层。