公开(公告)号：US06370012B1

公开(公告)日：2002-04-09

申请号：US09652596

申请日：2000-08-30

Applicant: Sylvia Adae-Amoakoh ,  John M. Lauffer ,  Michael D. Lowell ,  Voya R. Markovich ,  Joseph J. Sniezek

Inventor： Sylvia Adae-Amoakoh ,  John M. Lauffer ,  Michael D. Lowell ,  Voya R. Markovich ,  Joseph J. Sniezek

IPC: H01G4228

CPC classification number: H05K1/053 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/162 ,  H05K3/403 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0338 ,  H05K2201/0919 ,  H05K2201/10378 ,  H05K2203/0315 ,  Y10T29/417 ,  H01L2924/00

Abstract: A parallel capacitor structure capable of forming an internal part of a larger circuit board or the like structure to provide capacitance therefore. Alternatively, the capacitor may be used as an interconnector to interconnect two different electronic components (e.g., chip carriers, circuit boards, and even semiconductor chips) while still providing desired levels of capacitance for one or more of said components. The capacitor includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor, and inorganic dielectric material (preferably an oxide layer on the second conductor layer's outer surfaces or a suitable dielectric material such as barium titanate applied to the second conductor layers). Further, the capacitor includes outer conductor layers atop the inorganic dielectric material, thus forming a parallel capacitor between the internal and added conductive layers and the outer conductors.

Abstract translation: 能够形成较大的电路板或类似结构的内部部分以提供电容的并联电容器结构。 或者，电容器可以用作互连器以互连两个不同的电子部件（例如，芯片载体，电路板，甚至半导体芯片），同时仍然为一个或多个所述部件提供期望的电容水平。 电容器包括至少一个内部导电层，在内部导体的相对侧上添加两个附加的导体层，以及无机介电材料（优选地，在第二导体层的外表面上的氧化物层或适用于诸如钛酸钡的适当介电材料 第二导体层）。 此外，电容器包括无机介电材料顶部的外部导体层，从而在内部和附加的导电层和外部导体之间形成并联的电容器。

公开(公告)号：US06339197B1

公开(公告)日：2002-01-15

申请号：US09579270

申请日：2000-05-26

Applicant: Takashi Fushie ,  Takeshi Kagatsume ,  Shigekazu Matsui

Inventor： Takashi Fushie ,  Takeshi Kagatsume ,  Shigekazu Matsui

IPC: H01R1204

CPC classification number: H05K3/426 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49165 ,  Y10T428/24926 ,  H01L2924/00

Abstract: A multilayer printed wiring board which permits the formation of fine wiring patterns, thereby increasing the density of wiring patterns. Using photosensitive glass having a coefficient of thermal expansion close to that of a copper film as a core substrate, a through hole is formed in the photosensitive glass by photolithography, a sputtering silicon oxide layer and a sputtering silicon nitride layer are formed to prevent leak of alkali metal ions from the photosensitive glass, a sputtering chromium layer, a sputtering chromium-copper layer and a sputtering copper layer are formed to enhance the adhesion strength between the copper film and the sputtering silicon oxide layer, and a copper film of 1 to 20 &mgr;m thick is formed. With resin filled into the interior of the through hole, a wiring layer is patterned by etching, an insulating layer is formed, and the surface is covered with a surface treatment layer and a cover coat.

Abstract translation: 允许形成精细布线图案的多层印刷布线板，从而增加布线图案的密度。 使用具有与铜膜接近的热膨胀系数的感光性玻璃作为芯基板，通过光刻在感光性玻璃中形成通孔，形成溅射氧化硅层和溅射氮化硅层，以防止泄漏 形成来自感光玻璃的碱金属离子，溅射铬层，溅射铬 - 铜层和溅射铜层，以提高铜膜和溅射氧化硅层之间的粘合强度，并使铜膜为1〜20 形成了厚厚的妈妈。 当树脂填充到通孔的内部时，通过蚀刻对布线层进行图案化，形成绝缘层，并且表面被表面处理层和覆盖层覆盖。

公开(公告)号：US06323096B1

公开(公告)日：2001-11-27

申请号：US09162800

申请日：1998-09-29

Applicant: Richard Joseph Saia ,  Kevin Matthew Durocher ,  Herbert Stanley Cole

Inventor： Richard Joseph Saia ,  Kevin Matthew Durocher ,  Herbert Stanley Cole

IPC: H01L2170

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/19 ,  H01L24/82 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/162 ,  H05K1/167 ,  H05K3/388 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315 ,  H05K2203/0361 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide. If the resistor and metallization layers are applied over both surfaces of the dielectric film, passive components can be fabricated on both surfaces of the dielectric film. The dielectric film can have vias therein with the resistor and metallization layers extending through the vias. A circuit chip can be attached and coupled to the passive components by metallization patterned through vias in an additional dielectric layer.

Abstract translation: 制造柔性互连膜的方法包括在电介质膜的一个或两个表面上施加电阻层; 在所述电阻层上施加金属化层，所述电阻层包括促进所述电介质膜和所述金属化层的粘附的材料; 在所述金属化层上施加电容器电介质层; 以及在电容器电介质层上施加电容器电极层。 将电容器电极层图案化以形成第一电容器电极; 对电容器电介质层进行图案化; 图案化金属化层以形成电阻器; 并且金属化层和电阻层被图案化以形成电感器和第二电容器电极。 在一个实施例中，电介质膜包括聚酰亚胺，电阻层包括氮化钽，电容器介电层包括无定形氢化碳或氧化钽。 如果将电阻和金属化层施加在电介质膜的两个表面上，则可以在电介质膜的两个表面上制造无源元件。 电介质膜可以具有通孔，其中电阻器和金属化层延伸穿过通孔。 电路芯片可以通过在附加电介质层中通过通孔图案化的金属化而附接并耦合到无源部件。

公开(公告)号：US06316737B1

公开(公告)日：2001-11-13

申请号：US09393952

申请日：1999-09-09

Applicant: Michael D. Evans ,  James D. Goss ,  Jeffrey A. Curhan ,  Patrizio Vinciarelli

Inventor： Michael D. Evans ,  James D. Goss ,  Jeffrey A. Curhan ,  Patrizio Vinciarelli

IPC: H05K116

CPC classification number: H05K1/111 ,  H01L2224/48091 ,  H01L2924/01079 ,  H05K1/0306 ,  H05K1/182 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0179 ,  H05K2201/09572 ,  H05K2201/09745 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2203/0455 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014

Abstract: In general, in one aspect, the invention features a connection between a through-hole in a circuit board and a contact region on a component. The contact region has a surface bearing a depression. A continuous solder column has one end of that forms a solder joint with an inner wall of the through-hole and the other end of that forms a solder joint with the contact region.

Abstract translation: 通常，一方面，本发明的特征在于电路板中的通孔与部件上的接触区域之间的连接。 接触区域具有带凹陷的表面。 连续的焊料柱的一端与通孔的内壁形成焊接点，另一端与接触区域形成焊接点。

公开(公告)号：US5509200A

公开(公告)日：1996-04-23

申请号：US342506

申请日：1994-11-21

Applicant: Jerome A. Frankeny ,  Richard F. Frankeny ,  Ronald L. Imken ,  Keith A. Vanderlee

Inventor： Jerome A. Frankeny ,  Richard F. Frankeny ,  Ronald L. Imken ,  Keith A. Vanderlee

IPC: H01L23/538 ,  H05K1/11 ,  H05K1/16 ,  H05K3/00 ,  H05K3/44 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/462 ,  H01L23/5385 ,  H05K1/112 ,  H05K1/162 ,  H05K3/445 ,  H05K3/4641 ,  H01L2224/16225 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/0373 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10378 ,  H05K2203/0307 ,  H05K3/0023 ,  H05K3/0094 ,  H05K3/4623 ,  Y10S428/901 ,  Y10T29/49165

Abstract: Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric, and has selectively deposited a metallic layer for interconnecting the capacitor and forming vias. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability.

Abstract translation: 用于制造精细间距图案多层印刷电路板的方法和装置，其包括提供功率分配，信号分配和电容去耦的层叠堆叠板层。 在一个方面，本发明涉及通过金属芯开始制造板层，图案化芯，选择性地将芯包围在电介质中，选择性地沉积金属以形成通孔，插塞和信号线，以及用连接冶金形成树突 在通孔和插头上，以从板层的平面上方或下方提供可堆叠连接。 在另一方面，本发明涉及使用溶胶 - 凝胶法在金属片上形成薄的高介电常数结晶膜，随后在高介电常数膜上沉积金属层。 该膜用作电容器层的电介质，其后连续地被图案化，被电介质覆盖，并且已经选择性地沉积用于互连电容器和形成通孔的金属层。 然后通孔的端部经历树枝状生长并连接冶金以提供可堆叠的互连能力。

公开(公告)号：US5412160A

公开(公告)日：1995-05-02

申请号：US212869

申请日：1994-03-15

Applicant: Takaaki Yasumoto ,  Nobuo Iwase ,  Kaoru Koiwa ,  Koji Yamakawa ,  Kiyoshi Iyogi

Inventor： Takaaki Yasumoto ,  Nobuo Iwase ,  Kaoru Koiwa ,  Koji Yamakawa ,  Kiyoshi Iyogi

IPC: H01L23/373 ,  H05K1/02 ,  H05K1/00

CPC classification number: H01L23/3731 ,  H01L23/3732 ,  H01L23/3733 ,  H05K1/024 ,  H05K3/4605 ,  H05K3/467 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2201/0116 ,  H05K2201/0179

Abstract: A circuit board comprising a substrate, at least one dielectric film formed on the substrate and made of at least one selected from the group consisting of AlN, BN, diamond, diamond-like carbon, BeO and SiC, the dielectric film having pores of a porosity of 5 to 95% by volume, and at least one wiring metal film formed on the dielectric film.

Abstract translation: 一种电路板，包括基板，至少一个电介质膜，形成在基板上，由选自AlN，BN，金刚石，类金刚石碳，BeO和SiC中的至少一种制成，电介质膜具有孔 5〜95体积％的孔隙率和形成在电介质膜上的至少一个布线金属膜。

公开(公告)号：US5272600A

公开(公告)日：1993-12-21

申请号：US939228

申请日：1992-09-02

Applicant: David H. Carey

Inventor： David H. Carey

IPC: H01L23/538 ,  H01L23/64 ,  H05K1/00 ,  H05K1/11 ,  H05K1/16 ,  H05K1/14

CPC classification number: H05K1/162 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/64 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0289 ,  H05K1/115 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09345

Abstract: The invention relates to an electrical interconnect device with power and ground lines interwoven about signal line layers and capacitive vias between signal layers so as to make efficient use of otherwise undedicated area between signal lines and signal layers and to reduce or eliminate the need for separate power and ground layers while providing decoupling capacitance within the wiring structure.

Abstract translation: 本发明涉及一种具有电源和地线的电互连装置，其中信号线层和信号层之间的电容通孔交织在一起，以便有效地利用信号线和信号层之间的未被接合的区域，并减少或消除对分离电力的需要 和接地层，同时在布线结构内提供去耦电容。

公开(公告)号：US5196376A

公开(公告)日：1993-03-23

申请号：US662748

申请日：1991-03-01

Applicant: John J. Reche

Inventor： John J. Reche

IPC: H01L21/312 ,  H01L21/3213 ,  H01L21/48 ,  H05K3/00 ,  H05K3/06

CPC classification number: H05K3/061 ,  H01L21/312 ,  H01L21/32139 ,  H01L21/4846 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2203/0554 ,  H05K2203/107 ,  H05K3/0041 ,  Y10S438/94

Abstract: A laser lithography process for semiconductor interconnect and semiconductor manufacture having the advantages of non-contact printing processes and being much faster than prior art laser lithography processes is disclosed. In accordance with the process, a metal layer to be patterned either for use as a patterned metal layer or as a mask for patterning a layer therebelow, such as a think polyimide layer, is first coated with a very thin layer of polymer evaporated as a monomer using a vapor deposition process. This provides a very thin layer of polymer over the metal layer, which thin polymer layer is readily and quickly patterned by laser to provide a mask for the subsequent chemical etching of the metal layer. The vapor deposited polymer layer, while being very thin and thus readily removed by laser, is also substantially fault free, thereby providing a high-quality mask for the chemical etching process free of any possible damage from ordinary sources such as mask aligners, etc., yet being readily removed when desired such as by way of example, by plasma etching thereof. Various methods and applications are disclosed.

Abstract translation: 公开了一种用于半导体互连和半导体制造的激光光刻工艺，其具有非接触印刷工艺的优点并且比现有技术的激光光刻工艺快得多。 根据该方法，首先将要被图案化的图案化的金属层用作图案化金属层或作为用于图案化层的掩模，例如思亚酰胺层，涂覆有非常薄的作为 单体使用气相沉积工艺。 这在金属层上提供了非常薄的聚合物层，该薄层聚合物层通过激光容易且快速地构图，以提供用于金属层的后续化学蚀刻的掩模。 气相沉积聚合物层虽然非常薄且因此容易通过激光去除，但也基本上是无缺陷的，从而为化学蚀刻工艺提供了高质量的掩模，没有普通来源（例如掩模对准器等）的任何可能的损坏。 ，但是如果需要的话，例如通过等离子体蚀刻就容易除去。 公开了各种方法和应用。

公开(公告)号：US4946549A

公开(公告)日：1990-08-07

申请号：US428137

申请日：1989-10-27

Applicant: Bonnie J. Bachman ,  Elizabeth A. Hofstatter ,  Joan M. Ritter ,  Jerry J. Rubin

Inventor： Bonnie J. Bachman ,  Elizabeth A. Hofstatter ,  Joan M. Ritter ,  Jerry J. Rubin

IPC: G03F7/42 ,  H05K3/28

CPC classification number: H05K3/288 ,  G03F7/427 ,  H05K2201/0179 ,  H05K2203/0769 ,  H05K2203/095 ,  H05K3/28

Abstract: Disclosed is a method for removing poly-para-xylylene, its derivatives, and copolymers (collectively called "parylene") from bodies, including relatively large bodies such as printed circuit (PC) boards, that is capable of yielding relatively high removal rates. A body such as a PC board coated with parylene is placed into a reaction chamber downstream from a microwave plasma such that plasma discharge products generated by the microwave plasma react with the parylene, etching the parylene without exposing the body to bombardment by energetic ions and/or electrons. The plasma is generated from a gas mixture containing oxygen, a second gas, and optional additives such as N.sub.2 O, He,or Ar. The second gas is selected from the group consisting of fluorocarbons, fluorosulfides, and chlorofluorocarbons. A currently preferred second gas is CFR.sub.4. The inventive method is also applicable for fabricating articles such as integrated circuits and semiconductor devices that comprise a parylene layer.

Abstract translation: 公开了一种从体内除去聚对二甲苯，其衍生物和共聚物（统称为“聚对二甲苯”）的方法，其包括能够产生相对高的去除速率的相对较大的体（例如印刷电路板）。 将诸如涂有聚对二甲苯的PC板的主体放置在微波等离子体下游的反应室中，使得由微波等离子体产生的等离子体放电产物与聚对二甲苯反应，蚀刻聚对二甲苯，而不会使身体暴露于能量离子和/ 或电子。 等离子体由含有氧气，第二气体和任选的添加剂如N2O，He或Ar的气体混合物产生。 第二气体选自碳氟化合物，氟代硫化物和氯氟化碳。 目前优选的第二气体是CFR4。 本发明的方法也适用于制造诸如集成电路和包含聚对二甲苯层的半导体器件的制品。

公开(公告)号：US4598022A

公开(公告)日：1986-07-01

申请号：US707992

申请日：1985-03-04

Applicant: Reza Haque ,  Edward F. Smith, III ,  Igor V. Kadija

Inventor： Reza Haque ,  Edward F. Smith, III ,  Igor V. Kadija

IPC: B05D7/24 ,  H05K3/38 ,  B05D3/06 ,  B05D5/10

CPC classification number: B05D1/62 ,  H05K3/386 ,  B05D2202/45 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2203/095 ,  H05K3/382 ,  Y10T428/31511 ,  Y10T428/31678 ,  Y10T428/31696 ,  Y10T428/31721

Abstract: A one-step plasma treatment for improving the laminate adhesion of metallic and non-metallic substrates is described. The treatment comprises forming a plasma of a polar containing organic species and at least one of nitrogen and hydrogen and exposing a substrate material to the plasma for a period of time sufficient to deposit a polymeric film on at least one surface. In a preferred embodiment, a plasma of an azole, nitrogen and/or hydrogen is utilized. The process has particular utility in forming adherent polymeric films on one or more surfaces of copper and copper alloy foils to be used in printed circuit applications.

Abstract translation: 描述了用于改善金属和非金属基底的层压粘合性的一步等离子体处理。 处理包括形成极性含有有机物质的等离子体和氮和氢中的至少一种，并将基材材料暴露于等离子体一段足以在至少一个表面上沉积聚合物膜的时间。 在优选的实施方案中，使用了唑，氮和/或氢的等离子体。 该方法在用于印刷电路应用的铜和铜合金箔的一个或多个表面上形成粘附聚合物膜具有特别的用途。