公开(公告)号：US20060169484A1

公开(公告)日：2006-08-03

申请号：US11304770

申请日：2005-12-16

Applicant: Takahiro Yamashita ,  Hiroyuki Watanabe ,  Kiyotaka Tsukada ,  Michio Ido ,  Morio Nakao

Inventor： Takahiro Yamashita ,  Hiroyuki Watanabe ,  Kiyotaka Tsukada ,  Michio Ido ,  Morio Nakao

IPC: H05K1/18 ,  H05K3/34

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/3457 ,  H05K2201/0347 ,  H05K2201/09436 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/098 ,  Y10T29/49144 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: This invention provides a printed wiring board having an intensified drop impact resistance of a joint portion between pad and solder. An electrode pad comprises pad portion loaded with solder ball and a cylindrical portion projecting to the solder ball supporting the pad portion. An outer edge of the pad portion extends sideway from a cylindrical portion so that the outer edge is capable of bending. If the outer edge bends when stress is applied to the solder ball 30, stress on the outer edge of the pad portion on which stress is concentrated can be relaxed so as to intensify the joint strength between an electrode pad and solder ball.

Abstract translation: 本发明提供了一种印刷电路板，其具有焊盘和焊料之间的接合部分的强烈的耐滴落冲击性。 电极焊盘包括装载有焊球的焊盘部分和突出到支撑焊盘部分的焊球的圆柱形部分。 衬垫部分的外边缘从圆筒部分侧向延伸，使得外边缘能够弯曲。 如果当对焊球30施加应力时外边缘弯曲，则可以放松应力集中的焊盘部分的外边缘上的应力，以增强电极焊盘和焊球之间的接合强度。

公开(公告)号：US07083901B2

公开(公告)日：2006-08-01

申请号：US10262724

申请日：2002-10-01

Applicant: Frank D. Egitto ,  Voya Markovich ,  Thomas R. Miller ,  Douglas O. Powell ,  James R. Wilcox

Inventor： Frank D. Egitto ,  Voya Markovich ,  Thomas R. Miller ,  Douglas O. Powell ,  James R. Wilcox

IPC: G03C5/00 ,  H01K3/00

CPC classification number: H05K3/4069 ,  H05K3/062 ,  H05K3/108 ,  H05K3/423 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4614 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09554 ,  H05K2203/025 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1461 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49179

Abstract: A layer for use in a modular assemblage for supporting ICES is formed with metal contacts for assembly by making a sandwich of metal interconnect members between two layers of dielectric; drilling holes through the dielectric, stopping on a metal layer bonded to the bottom surface of the module; forming blind holes stopping on the interconnect members; and plating metal through the volume of the via, both full and blind holes, thereby forming vertical and horizontal connections in a layer that be stacked to form complex interconnect assemblies.

Abstract translation: 用于支撑ICES的模块化组件中的层由用于组装的金属触点形成，通过在两层电介质之间制造金属互连构件的夹层; 通过电介质钻孔，停止在与模块底面接合的金属层上; 形成在所述互连构件上停止的盲孔; 并通过通孔的体积电镀金属孔，这两个孔都是盲孔，从而在堆叠形成复杂互连组件的层中形成垂直和水平连接。

公开(公告)号：US07071423B2

公开(公告)日：2006-07-04

申请号：US10915483

申请日：2004-08-11

Applicant: James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich

Inventor： James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich

IPC: H05K1/00 ,  H01R12/04

CPC classification number: H05K3/462 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

Abstract translation: 电路化基板组件及其制造方法，其中所述组件包括结合在一起的单独的电路化基板。 基板各自包括至少一个开口，其中仅一个开口在接合之前基本上填充有导电浆料。 一旦粘合，糊料也部分地位于另一个开口内，以提供与其的有效电连接。

公开(公告)号：US20060123626A1

公开(公告)日：2006-06-15

申请号：US11349998

申请日：2006-02-09

Applicant: James Fuller ,  John Lauffer ,  Voya Markovich

Inventor： James Fuller ,  John Lauffer ,  Voya Markovich

IPC: H05K3/36

CPC classification number: H05K3/462 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A method of making a circuitized substrate assembly wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, and a cover is placed over one of the openings and a quantity of conductive paste is positioned thereon prior to bonding the substrates. At least some of the paste is then forced up into an opening in the other substrate as a result of the bonding.

Abstract translation: 一种制造电路化基板组件的方法，其中所述组件包括结合在一起的各个电路化基板。 基板各自包括至少一个开口，并且在其上面的一个开口上放置盖子，并且在粘合基板之前将一定数量的导电浆料放置在其上。 因此，粘合剂的至少一部分然后被迫上升到另一个基底中的开口中。

公开(公告)号：US07060912B2

公开(公告)日：2006-06-13

申请号：US10310803

申请日：2002-12-06

Applicant: Mitsunori Nagashima ,  Tomoyoshi Hiei

Inventor： Mitsunori Nagashima ,  Tomoyoshi Hiei

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/3405 ,  H05K1/113 ,  H05K3/3421 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/1028 ,  H05K2201/1034 ,  Y10T29/49165

Abstract: A circuit board comprises a board substrate including a substrate layer formed with a pad on an upper surface thereof, and a metal piece soldered on the pad. At least one through-hole including an internal wall formed with a conductive film is provided at a portion corresponding to the pad on the substrate layer. The through-hole is filled with a predetermined filler for closing at least an open mouth of the through-hole at the upper surface of the substrate layer. The pad is connected integrally with the conductive film on the internal wall of the through-hole.

Abstract translation: 一种电路板包括一个板基板，该基板包括一个在其上表面上形成有一个焊盘的基板层，以及一个焊接在焊盘上的金属片。 至少一个包括形成有导电膜的内壁的通孔设置在与衬底层上的衬垫相对应的部分。 填充有用于在基材层的上表面封闭通孔的至少一个开放口的预定填料。 衬垫与通孔内壁上的导电膜一体连接。

公开(公告)号：US07060418B2

公开(公告)日：2006-06-13

申请号：US10477689

申请日：2002-05-23

Applicant: Christophe Mathieu

Inventor： Christophe Mathieu

IPC: G03F7/00 ,  B41F31/00

CPC classification number: H05K3/246 ,  G06K19/07779 ,  G06K19/07783 ,  H05K1/095 ,  H05K1/165 ,  H05K3/1275 ,  H05K3/245 ,  H05K2201/0347 ,  H05K2203/0113 ,  H05K2203/0143 ,  H05K2203/0534 ,  H05K2203/1545 ,  H05K2203/1572

Abstract: In a method for the manufacture of a printed circuit on a dielectric carrier (2), in a first step a circuit pattern (1) is applied with an electrically conductive ink and, in a second step, the circuit model is plated, the electrically conductive ink being applied by means of a method of gravure printing and the plating being done by electrolytic or chemical means.

Abstract translation: 在用于在电介质载体（2）上制造印刷电路的方法中，在第一步骤中，对电路图案（1）施加导电油墨，并且在第二步中，电路模型被电镀，电 通过凹版印刷的方法施加导电油墨，并且通过电解或化学方法进行电镀。

公开(公告)号：US20060120014A1

公开(公告)日：2006-06-08

申请号：US11272781

申请日：2005-11-15

Applicant: Hirofumi Nakamura ,  Yutaka Akimoto ,  Sadamu Toita ,  Takayuki Inoi ,  Katsuhiro Yoshida

Inventor： Hirofumi Nakamura ,  Yutaka Akimoto ,  Sadamu Toita ,  Takayuki Inoi ,  Katsuhiro Yoshida

IPC: H01G9/00 ,  H01G4/008

CPC classification number: H01G9/025 ,  H01G9/15 ,  H05K1/162 ,  H05K2201/0329 ,  H05K2201/0347 ,  H05K2201/035 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0315 ,  Y10T29/417

Abstract: A sheet-shaped capacitor for storing electrical charges of large capacities, and to assure facilitated manufacture, cost reduction and improved reliability, and a method for manufacturing the capacitor. The capacitor includes a dielectric film 12, formed on a first major surface of a metal plate 11, an electrically conductive high polymer layer 13, formed on a first major surface of the dielectric film, and an electrically conductive layer 14 formed on a first major surface of the electrically conductive high polymer layer 13, such as by copper plating. A cathode electrode 20 is led out from the electrically conductive layer 14 on the side electrically conductive high polymer layer 13.

Abstract translation: 一种用于存储大容量的电荷并且确保便于制造，降低成本和提高可靠性的片状电容器以及用于制造电容器的方法。 电容器包括形成在金属板11的第一主表面上的电介质膜12，形成在电介质膜的第一主表面上的导电高分子层13和形成在第一主体上的导电层14 导电高分子层13的表面，例如通过镀铜。 在导电性高分子层13的导电层14上引出阴极电极20。

公开(公告)号：US20060118804A1

公开(公告)日：2006-06-08

申请号：US11294539

申请日：2005-12-06

Applicant: Makoto Nagai ,  Setsuo Yada ,  Atsushi Uchida

Inventor： Makoto Nagai ,  Setsuo Yada ,  Atsushi Uchida

IPC: H01L33/00

CPC classification number: H05K1/183 ,  H01L33/486 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/32225 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/246 ,  H05K3/4614 ,  H05K3/4629 ,  H05K3/4697 ,  H05K2201/0347 ,  H05K2201/09836 ,  H05K2201/09981 ,  H05K2201/10106 ,  H05K2203/061

Abstract: A wiring substrate for mounting a light emitting element, comprising: a substrate body comprising an insulating material and having a first surface and a back surface; and a cavity being opened into the first surface of said substrate body and having a mounting area for mounting a light emitting element at a bottom face of said cavity, wherein a metallized layer provided along a side face of said cavity and metallized layers provided in said substrate body are provided to continue to each other.

Abstract translation: 一种用于安装发光元件的布线基板，包括：基板主体，包括绝缘材料并具有第一表面和后表面; 并且腔体被打开到所述基板主体的第一表面中并且具有用于将发光元件安装在所述空腔的底面的安装区域，其中沿着所述腔体的侧面设置的金属化层和设置在所述腔体中的金属化层 衬底本体被设置成彼此连续。

公开(公告)号：US20060065438A1

公开(公告)日：2006-03-30

申请号：US11231746

申请日：2005-09-22

Applicant: Kouki Yamamoto

Inventor： Kouki Yamamoto

IPC: H05K1/18

CPC classification number: H05K3/3442 ,  H05K1/111 ,  H05K3/243 ,  H05K3/244 ,  H05K3/284 ,  H05K3/4015 ,  H05K2201/0209 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/09481 ,  H05K2201/0959 ,  H05K2201/09736 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: A circuit component mounting device includes a resin substrate, vias, a circuit component composed of a main body and electrode portions, a solder, and an insulative sealing resin that covers the circuit component and the solder. The device further includes a base metal pattern which covers parts of the principal face of the resin substrate where the vias are exposed and is composed of a Cu layer and a Ni layer and a copper plated pattern which is provided on the base metal pattern and is composed of a Cu layer, a Ni layer, and an Au layer. The circuit component is provided on the copper plated pattern. The solder allows the copper plated pattern and the circuit component to adhere to each other.

Abstract translation: 电路部件安装装置包括树脂基板，通孔，由主体和电极部分组成的电路部件，焊料和覆盖电路部件和焊料的绝缘密封树脂。 该装置还包括基体金属图案，其覆盖树脂基板的主要面的部分，其中通孔露出，并且由Cu层和Ni层构成，并且镀铜图案设置在基底金属图案上，并且是 由Cu层，Ni层和Au层构成。 电路元件设置在镀铜图案上。 焊料允许镀铜图案和电路部件彼此粘附。

公开(公告)号：US20060065434A1

公开(公告)日：2006-03-30

申请号：US11148893

申请日：2005-06-08

Applicant: Chi-Hsing Hsu ,  Hsing-Chou Hsu

Inventor： Chi-Hsing Hsu ,  Hsing-Chou Hsu

IPC: H05K1/11

CPC classification number: H05K1/0216 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/093 ,  H05K2201/0959 ,  H05K2201/09718

Abstract: A signal transmission structure suitable for a multi-layer circuit substrate comprising a core layer and at least a dielectric layer is provided. The signal transmission structure according to the present invention comprises a first via landing pad and a reference plane. The first via landing pad is disposed on a first surface of the core layer, and covering one end of the through hole of the core layer. The dielectric layer covers the first via landing pad and the first surface of the core layer. And the first reference plane is disposed above the dielectric layer, having a first opening disposed above one end of the through hole. Wherein, the area where the first reference plane is projected on the first surface of the core layer does not overlap with the area where the first via landing pad is projected on the first surface of the core layer.

Abstract translation: 提供适用于包括芯层和至少介电层的多层电路基板的信号传输结构。 根据本发明的信号传输结构包括第一通孔着陆垫和参考平面。 第一通孔着陆垫设置在芯层的第一表面上，并且覆盖芯层的通孔的一端。 电介质层覆盖第一通孔着陆焊盘和芯层的第一表面。 并且第一参考平面设置在电介质层上方，具有设置在通孔一端的第一开口。 其中，第一参考平面投影在芯层的第一表面上的区域不与第一通孔着陆垫投射在芯层的第一表面上的区域重叠。