公开(公告)号：US20110094782A1

公开(公告)日：2011-04-28

申请号：US12647395

申请日：2009-12-25

Applicant: HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

Inventor： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC: H05K1/16

CPC classification number: H05K1/0253 ,  H05K1/181 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A printed circuit board includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the signal transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path. A length of a first axis, perpendicular to the signal transmission line, of the void satisfies a following equation: W 1 ≈ 8  Wpad + 10  T 0.8  Wtrace + T , wherein Wpad is a width of the pad, Wtrace is a width of the transmission line, T is the height of the pad.

Abstract translation: 印刷电路板包括信号平面和参考平面。 信号平面包括焊盘，安装在焊盘上的无源元件以及通过焊盘与无源元件电连接的信号传输线。 参考平面为通过无源元件和信号传输线传输的信号提供返回路径。 在对应于无源元件的参考平面中定义空隙，以增加返回路径的长度。 垂直于信号传输线的第一轴的长度满足以下等式：W 1≈8 Wpad + 10 T T W W W T T T + T，其中W pad是焊盘的宽度，Wtrace是 传输线的宽度，T是焊盘的高度。

公开(公告)号：US07928560B2

公开(公告)日：2011-04-19

申请号：US12780501

申请日：2010-05-14

Applicant: Masashi Miyazaki ,  Mitsuhiro Takayama ,  Tatsuro Sawatari

Inventor： Masashi Miyazaki ,  Mitsuhiro Takayama ,  Tatsuro Sawatari

IPC: H01L23/04

CPC classification number: H05K1/185 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/021 ,  H05K3/445 ,  H05K3/4641 ,  H05K2201/0969 ,  H05K2201/09745 ,  H01L2924/00

Abstract: A composite multi-layer substrate comprising a flat plate-like core member formed of a material having an excellent electric conductivity, an excellent heat conductivity, and a high rigidity, a front resin layer and a rear resin layer covering at least the front and rear surfaces of the core member, and a bottomless hole formed in the core member through the front and rear sides of the core member, wherein an electronic component is installed in the bottomless hole, whereby since the strength of the composite multi-layer substrate can be assured by the rigidity of the core member, conventional prior art glass cloth can be eliminated, deterioration in the electric characteristics caused by ion migration can be avoided and will result in reduced production cost.

Abstract translation: 一种复合多层基板，包括由具有优异导电性，优异导热性和高刚性的材料形成的平板状芯体，至少覆盖前后树脂层和后树脂层 芯构件的表面和通过芯构件的前后侧形成在芯构件中的无底孔，其中电子部件安装在无底孔中，由此，复合多层基板的强度可以 通过芯构件的刚性保证，可以消除传统的现有技术的玻璃布，可以避免由离子迁移引起的电特性的劣化，并且将导致降低生产成本。

公开(公告)号：US07923907B2

公开(公告)日：2011-04-12

申请号：US12355881

申请日：2009-01-19

Applicant: Thomas Tessnow ,  Kim Albright ,  Michael Tucker

Inventor： Thomas Tessnow ,  Kim Albright ,  Michael Tucker

IPC: F21V29/00 ,  F21S4/00 ,  H01J1/62

CPC classification number: F21V29/70 ,  F21K9/00 ,  F21S41/141 ,  F21S41/192 ,  F21S43/14 ,  F21S43/195 ,  F21S45/47 ,  F21S45/49 ,  F21S45/50 ,  F21V29/89 ,  F21W2103/00 ,  F21Y2107/90 ,  F21Y2115/10 ,  H05K1/0203 ,  H05K3/0061 ,  H05K3/28 ,  H05K2201/0969 ,  H05K2201/10106 ,  H05K2201/1034 ,  H05K2201/10598 ,  H05K2203/1572 ,  Y10S362/80

Abstract: A robust LED lamp may be assembly by forming a heat sinking sandwich with two metal heat sinks positioned around the circuit board and pinned together a heat conductive element. The assembly is positioned by pressing it into a base providing electrical connections. The robust assembly is rapidly assembled, thermally effective in draining or spreading heat from the circuit board and is readily adaptable to a variety of applications lighting. The heat sink may be decorated, colored or otherwise esthetically enhanced for consumer appreciation.

Abstract translation: 强大的LED灯可以通过形成散热夹层而组装，其中两个金属散热器位于电路板周围并且将导热元件固定在一起。 组件通过将其压入提供电连接的基座来定位。 坚固的组件被快速组装，热效率地从电路板排出或散布热量，并且容易适用于各种应用照明。 散热器可以装饰，着色或以其他方式美观地加强，以便消费者欣赏。

公开(公告)号：US07906374B2

公开(公告)日：2011-03-15

申请号：US12057387

申请日：2008-03-28

Applicant: Chiu-Shun Lin ,  Pai-Sheng Cheng

Inventor： Chiu-Shun Lin ,  Pai-Sheng Cheng

IPC: H01L21/00

CPC classification number: H01L23/4985 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H05K1/0209 ,  H05K1/189 ,  H05K3/303 ,  H05K2201/0108 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2203/166 ,  Y02P70/613

Abstract: A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate and has a first designated pattern for bump bonding. The second conductive foil is disposed on the second surface of the substrate and has a second designated pattern, wherein the area of the second designated pattern is not smaller than the area of the first designated pattern.

Abstract translation: COF包装结构包括基板，第一导电箔和第二导电箔。 基板具有与第一表面相对的第一表面和第二表面。 第一导电箔设置在基板的第一表面上，并且具有用于凸起接合的第一指定图案。 第二导电箔设置在基板的第二表面上，并具有第二指定图案，其中第二指定图案的面积不小于第一指定图案的面积。

公开(公告)号：US20110057323A1

公开(公告)日：2011-03-10

申请号：US12876674

申请日：2010-09-07

Applicant: Kan-Jung Chia

Inventor： Kan-Jung Chia

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/50 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24227 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/185 ,  H05K3/0032 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening region predefined on the first surface; forming a first metallic frame around the periphery of the predefined opening region on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. The invention can precisely control the shape of the opening through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.

Abstract translation: 一种用于制造具有嵌入式半导体元件的封装结构的方法，包括：提供具有相反的第一表面和第二表面的基底和至少在第一表面上预定的开口区域; 在所述第一表面上形成围绕所述预定开口区域的周边的第一金属框架; 通过激光烧蚀在所述第一金属框架内部至少形成开口; 在开口处设置半导体芯片; 在所述第一和第二表面和所述芯片上形成第一电介质层; 在所述第一表面的所述第一介电层上形成第一布线层; 以及在第一介电层和第一表面的第一布线层上形成第一组合结构。 本发明可以精确地控制通过围绕预定开口区域的周边的第一金属框架的开口的形状，从而允许芯片被精确地嵌入到基板中。

公开(公告)号：US07875804B1

公开(公告)日：2011-01-25

申请号：US11535712

申请日：2006-09-27

Applicant: Jeffrey M. Tronnes ,  Cedar Decker ,  Brett L. Haugen

Inventor： Jeffrey M. Tronnes ,  Cedar Decker ,  Brett L. Haugen

IPC: H05K1/00

CPC classification number: G11B5/484 ,  G11B5/4853 ,  H05K1/056 ,  H05K3/244 ,  H05K3/421 ,  H05K3/44 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09554 ,  H05K2201/0969 ,  H05K2203/1184

Abstract: A method for forming an electrical interconnect on an integrated lead suspension or suspension component of the type having a stainless steel layer, a conductive lead layer and an insulator layer separating the stainless steel and conductive lead layers. An aperture is formed through only the insulator layer to expose the stainless steel layer at an interconnect site. An interconnect mask is applied around the interconnect site. A first conductive material is electroplated onto the stainless steel layer at the interconnect site to form a plated interconnect between the spring metal layer and the conductive lead layer. The mask is then removed. An electrical interconnect between the stainless steel and conductive lead layers including an aperture only through the insulator layer and an electroplated conductive material interconnect extending between both the spring metal layer and the conductive lead layer.

Abstract translation: 一种用于在具有不锈钢层，导电引线层和分离不锈钢和导电引线层的绝缘体层的类型的集成引线悬置或悬挂部件上形成电互连的方法。 仅通过绝缘体层形成孔，以在互连部位露出不锈钢层。 在互连站点周围应用互连掩模。 将第一导电材料电镀在互连部位的不锈钢层上，以在弹簧金属层和导电引线层之间形成电镀互连。 然后取下面具。 不锈钢和导电引线层之间的电互连包括仅通过绝缘体层的孔和在弹簧金属层和导电引线层之间延伸的电镀导电材料互连。

公开(公告)号：US07873933B2

公开(公告)日：2011-01-18

申请号：US11936673

申请日：2007-11-07

Applicant: Hubert Harrer ,  Andreas Huber ,  Thomas-Michael Winkel

Inventor： Hubert Harrer ,  Andreas Huber ,  Thomas-Michael Winkel

IPC: G06F17/50 ,  H03K17/693

CPC classification number: H05K1/0265 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10189 ,  Y10T29/49156

Abstract: A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract translation: 用于平衡印刷电路板（PWB）中的电源平面引脚电流的计算机程序提供了降低电源平面（包括接地平面）连接所需的引脚数量和/或减少每个引脚上连接器电流处理的要求。 在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。 连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。 槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。 所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

公开(公告)号：US20100314159A1

公开(公告)日：2010-12-16

申请号：US12866981

申请日：2008-11-21

Applicant: Yong Goo Lee ,  Kyoung il Kang

Inventor： Yong Goo Lee ,  Kyoung il Kang

IPC: H05K1/00 ,  H05K1/03

CPC classification number: H05K1/0253 ,  H05K1/0224 ,  H05K2201/0715 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/09781

Abstract: The present disclosure provides a printed circuit board (PCB) comprising a first ground layer extended in one direction a first dielectric layer laminated on the first ground layer and extended in the same direction as that of the first ground layer; a signal transmission line laminated on the first dielectric layer and extended in the same direction as that of the first dielectric layer; and a plurality of first ground patterns formed by etching a surface of the first ground layer in an axial direction thereof at a predetermined interval in a line, wherein the plurality of first ground patterns expose the first dielectric layer.

Abstract translation: 本公开提供一种印刷电路板（PCB），其包括在一个方向上延伸的第一电介质层，所述第一接地层层叠在所述第一接地层上并沿与所述第一接地层相同的方向延伸的第一电介质层; 层叠在所述第一电介质层上并沿与所述第一电介质层相同的方向延伸的信号传输线; 以及多个第一接地图案​​，其通过以一定的间隔在一条线上沿其轴向蚀刻第一接地层的表面而形成，其中多个第一接地图案​​暴露第一介电层。

公开(公告)号：US20100263462A1

公开(公告)日：2010-10-21

申请号：US12762510

申请日：2010-04-19

Applicant: Hidehiro NAKAMURA

Inventor： Hidehiro NAKAMURA

IPC: H05K1/00 ,  G01D21/00 ,  H01R43/02

CPC classification number: H05K13/00 ,  G01D1/00 ,  G01D15/00 ,  H05K1/028 ,  H05K1/118 ,  H05K3/3447 ,  H05K3/365 ,  H05K3/4602 ,  H05K3/4635 ,  H05K2201/09063 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2201/09109 ,  H05K2201/09127 ,  H05K2201/09163 ,  H05K2201/09318 ,  H05K2201/0969 ,  H05K2201/10151 ,  H05K2201/10189 ,  H05K2201/10598 ,  H05K2203/061 ,  H05K2203/167

Abstract: There is provided a method of manufacturing a concave connector substrate that has high connection accuracy, a low manufacturing cost, and high flexibility in design, can ensure stable repeated use, and significantly improve use convenience.A method of manufacturing a concave connector substrate includes: a step of preparing a guide substrate having a guide/holding region that guides a plate-shaped connector to a connection position and holds the plate-shaped connector at the connection position and a cut portion for removing a section having a shape corresponding to the guide/holding region on at least one side; a step of arranging and aligning two wiring substrates, each having wiring lines and through hole connection portions that are electrically connected to the wiring lines, with both surfaces of the guide substrate, and applying an adhesive to a predetermined region of the guide substrate to bond the wiring substrates to the guide substrate; a step of bending a portion of the wiring substrate toward the inside of the cut portion of the guide substrate and bringing the wiring lines disposed in the bent portion into pressure contact with the inside of the cut portion; and a step of removing a section inside the cut portion to form the guide/holding region.

Abstract translation: 提供了一种制造具有高连接精度，低制造成本和高设计灵活性的凹形连接器基板的方法，可以确保稳定的重复使用，并且显着提高使用方便性。 一种制造凹形连接器基板的方法包括：准备具有引导/保持区域的导向基板的步骤，该导向基板将板状连接器引导到连接位置并将板状连接器保持在连接位置， 在至少一个侧面上移除具有与所述引导/保持区域相对应的形状的部分; 在导向基板的两个表面上布置和对准两个布线基板，每个布线基板具有布线和与布线电连接的通孔连接部分，并且将粘合剂施加到引导基板的预定区域以键合 布线基板到引导基板; 将布线基板的一部分朝向引导基板的切断部的内侧弯曲并使配置在弯曲部的布线与切断部的内部压力接触的步骤; 以及去除切割部分内的部分以形成引导/保持区域的步骤。

公开(公告)号：US20100261346A1

公开(公告)日：2010-10-14

申请号：US12823316

申请日：2010-06-25

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H01L21/768 ,  G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract translation: 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括在通过空隙减少与信号承载PTH的耦合并且维持 信号路径导体。