公开(公告)号：US20060131069A1

公开(公告)日：2006-06-22

申请号：US11311568

申请日：2005-12-19

Applicant: Noriyoshi Shimizu ,  Tomoo Yamasaki ,  Kiyoshi Oi ,  Akio Rokugawa

Inventor： Noriyoshi Shimizu ,  Tomoo Yamasaki ,  Kiyoshi Oi ,  Akio Rokugawa

IPC: H05K1/16

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/025 ,  H05K3/4602 ,  H05K2201/0179 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: The present invention discloses a method of manufacturing a wiring substrate to which a semiconductor chip mounted. The method includes the steps of forming a base, forming a peeling layer on the base, forming a capacitor having a plurality of layers on the peeling layer, and forming a wiring part in the capacitor for connecting the capacitor to the semiconductor chip.

公开(公告)号：US07047628B2

公开(公告)日：2006-05-23

申请号：US10356660

申请日：2003-01-31

Applicant: Michael K. T. Lee

Inventor： Michael K. T. Lee

IPC: H05K3/36

CPC classification number: H05K1/0251 ,  H05K1/0219 ,  H05K1/0245 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/0949 ,  H05K2201/09718 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A printed wiring board having differential pair signal traces has increased spacing between signal-carrying vias and ground or power planes and/or is equipped with selectively placed ground vias to enhance the impedance matching of the signal traces.

Abstract translation: 具有差分对信号迹线的印刷电路板在信号承载通孔和接地或电源平面之间具有增加的间隔和/或配备有选择放置的接地通孔，以增强信号迹线的阻抗匹配。

公开(公告)号：US20050146390A1

公开(公告)日：2005-07-07

申请号：US10813952

申请日：2004-03-31

Applicant: Jae-Myung Baek

Inventor： Jae-Myung Baek

IPC: H01P5/02 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/0251 ,  H01P5/02 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09718

Abstract: A multi-layer substrate comprising: a plurality of metal layers, on each of which a predetermined printed-circuit pattern is formed; and at least one insulating layer formed between the metal layers, wherein the plurality of metal layers includes: at least two high-frequency signal layers for transmitting a high-frequency signal. At least one ground layer provides a ground for the other metal layers, and wherein at least one via hole is formed through the multi-layer substrate to connect the high-frequency signal layers to each other. An impedance-matching hole passes through the ground layer so as to provide a path through which the via hole passes, and wherein a distance between the via hole and the ground layer is adapted for adjustment by the impedance-matching hole to adjust capacitance, so that a quasi waveguide is formed and impedances in part of the hole are matched when a high-frequency signal is transmitted through the hole. Ground pads which are electrically connected to the ground layer and signal pads which are connected to the hole to help the adjustment of capacitance and increase matched bandwidth.

Abstract translation: 一种多层基板，包括：多个金属层，每个金属层上形成有预定的印刷电路图案; 以及在所述金属层之间形成的至少一个绝缘层，其中所述多个金属层包括：用于传输高频信号的至少两个高频信号层。 至少一个接地层为其它金属层提供接地，并且其中至少一个通孔形成穿过多层基板以将高频信号层彼此连接。 阻抗匹配孔穿过接地层，以提供通孔通过的路径，并且其中通孔和接地层之间的距离适于通过阻抗匹配孔调节以调整电容，因此 当高频信号通过孔传播时，形成准波导并且部分孔的阻抗匹配。 电连接到接地层的接地焊盘和连接到孔的信号焊盘，以帮助调整电容并增加匹配的带宽。

公开(公告)号：US20050128720A1

公开(公告)日：2005-06-16

申请号：US10736327

申请日：2003-12-15

Applicant: Robert Croswell ,  Gregory Dunn ,  Robert Lempkowski ,  Aroon Tungare ,  Jovica Savic

Inventor： Robert Croswell ,  Gregory Dunn ,  Robert Lempkowski ,  Aroon Tungare ,  Jovica Savic

IPC: H01G20060101 ,  H05K1/16 ,  H05K3/00 ,  H05K3/02 ,  H05K3/42 ,  H05K3/46 ,  H05K7/06

CPC classification number: H05K1/162 ,  H05K3/0029 ,  H05K3/025 ,  H05K3/384 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

Abstract translation: 嵌入印刷电路结构中的多个电容器之一包括覆盖印刷电路结构的第一衬底层（505）的第一电极（415），覆盖第一电极的结晶化电介质氧化物芯（405），第二电极 615），以及设置在结晶的电介质氧化物芯和第一和第二电极中的至少一个之间并与其接触的高温抗氧化剂层（220）。 结晶的电介质氧化物芯的厚度小于1微米，电容密度大于1000pF / mm 2。 多个电容器的材料和厚度相同。 结晶的电介质氧化物芯可以与多个电容器的所有其它电容器的结晶的电介质氧化物芯隔离。

公开(公告)号：US20050063165A1

公开(公告)日：2005-03-24

申请号：US10977263

申请日：2004-10-29

Applicant: Chi Chang ,  William Chen ,  Ajit Trivedi

Inventor： Chi Chang ,  William Chen ,  Ajit Trivedi

IPC: H01L23/498 ,  H05K1/02 ,  H05K3/34 ,  H05K7/12

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/09718 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.

Abstract translation: 本发明公开了提高使用底部填充封装的翻盖封装的可靠性的技术。 本发明的一个实施例描述了一种通过将封装衬底的中性平面远离其中间平面重新定位来封装倒装芯片的方法和装置。 本发明的另一个实施例描述了一种将层压板的层布置在用于PBGA封装中的方法和装置，其根据每层的刚度来布置层压板的层。 本发明的另一个实施例描述了一种在封装衬底的底部使用一个或多个冗余互连的倒装芯片的封装方法和装置，其中冗余互连在IC芯片的阴影之内。

公开(公告)号：US20040238216A1

公开(公告)日：2004-12-02

申请号：US10888064

申请日：2004-07-08

Inventor： Rebecca A. Jessep ,  Terrance J. Dishongh ,  Carolyn R. McCormick ,  Thomas O. Morgan

IPC: H05K001/03 ,  H05K001/11

CPC classification number: H05K1/024 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/445 ,  H05K2201/0187 ,  H05K2201/09309 ,  H05K2201/09581 ,  H05K2201/09718

Abstract: A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.

Abstract translation: 在印刷电路板的导电层中的间隙孔周围形成绝缘材料的保护涂层，使得间隙孔内的通路中的导电材料不会接触导电层并产生短路。 在一个实施例中，保护涂层足够难以偏转用于钻通孔的钻头，从而防止不配准的钻孔。

公开(公告)号：US06807065B2

公开(公告)日：2004-10-19

申请号：US10615378

申请日：2003-07-09

Applicant: Masahiro Sato

Inventor： Masahiro Sato

IPC: H05K702

CPC classification number: H05K1/0222 ,  H01P1/047 ,  H05K1/0237 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09336 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809 ,  Y10T428/24802 ,  Y10T428/24917

Abstract: A multilayer PCB has first and second signal transmission lines and first and second ground layers. A signal via is connected between the first and second transmission lines. Ground vias extending parallel to the signal via are connected between the first and second ground layers. The end of the first ground layer protrudes with respect to the second ground layer and extends nearer to the signal via than the second ground layer. Thus, it is possible to stabilize the characteristic impedance of the first transmission line.

Abstract translation: 多层PCB具有第一和第二信号传输线以及第一和第二接地层。 信号通孔连接在第一和第二传输线之间。 平行于信号通孔延伸的接地通孔连接在第一和第二接地层之间。 第一接地层的端部相对于第二接地层突出，并且比第二接地层更靠近信号通路延伸。 因此，可以稳定第一传输线的特性阻抗。

公开(公告)号：US06781064B1

公开(公告)日：2004-08-24

申请号：US09342584

申请日：1999-06-29

Applicant: Bernd K. Appelt ,  Anilkumar C. Bhatt ,  James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich ,  William J. Rudik ,  William E. Wilson

Inventor： Bernd K. Appelt ,  Anilkumar C. Bhatt ,  James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich ,  William J. Rudik ,  William E. Wilson

IPC: H05K103

CPC classification number: H01L23/564 ,  H01L21/481 ,  H01L23/498 ,  H01L23/49894 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/036 ,  H05K1/0366 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/0769 ,  H05K2201/09718 ,  H05K2201/09881 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.

Abstract translation: 一种用于诸如球栅阵列封装或有机芯片载体封装的电子器件封装中的印刷电路板。 该印刷电路板包括一个无玻璃的电介质，用于分离和绝缘电源芯，电路或电镀通孔，以防止导电材料沿玻璃基预浸料衬底迁移引起的短路。

公开(公告)号：US20030215619A1

公开(公告)日：2003-11-20

申请号：US10436143

申请日：2003-05-13

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kazuhiko Ooi ,  Masaru Yamazaki ,  Yukiji Watanabe ,  Takaaki Yazawa

IPC: B32B015/04

CPC classification number: H05K3/44 ,  H05K3/429 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09518 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09718 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09845 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A metal core substrate comprises a core layer (10) consisting of first and second metal plates (11, 12) layered with a third insulating layer (13) interposed therebetween; first and second insulating layers (20, 21) formed on the first and metal plates, respectively; first and second wiring patterns (45, 46) formed on the first and second insulating layers, respectively. A conductive layer (40) formed in a through-hole (22) penetrates the first insulating layer, the first metal plate, the third insulating layer, the second metal plate and the second insulating layer for electrically connecting the first wiring pattern with the second wiring pattern. The first metal plate (11) is electrically connected with the first wiring pattern (45) and the second wiring pattern (46), respectively, by means of a via (44) and by means a via (43). The second metal plate (12) is electrically connected with the second wiring pattern (46) and the first wiring pattern (45), respectively, by means of a via (42) and by means a via (41), respectively.

Abstract translation: 金属芯基板包括由第一和第二金属板（11,12）组成的芯层（10），第一和第二金属板与第三绝缘层（13）分开; 分别形成在第一和金属板上的第一和第二绝缘层（20,21）; 分别形成在第一和第二绝缘层上的第一和第二布线图案（45,46）。 形成在通孔（22）中的导电层（40）穿过第一绝缘层，第一金属板，第三绝缘层，第二金属板和第二绝缘层，用于将第一布线图案与第二绝缘层 接线图案。 第一金属板（11）通过通孔（44）和通孔（43）分别与第一布线图案（45）和第二布线图案（46）电连接。 第二金属板（12）分别通过通孔（42）和通孔（41）与第二布线图案（46）和第一布线图案（45）电连接。

公开(公告)号：US20010026444A1

公开(公告)日：2001-10-04

申请号：US09765413

申请日：2001-01-22

Inventor： Naoki Matsushima ,  Eiji Matsuzaki ,  Hidetaka Shigi ,  Yasunori Narizuka ,  Tetsuya Yamazaki ,  Kazuhiko Horikoshi ,  Yoichi Abe ,  Shosaku Ishihara ,  Kiyoshi Ogata ,  Toshiyuki Arai

IPC: H05K001/16

CPC classification number: H05K1/162 ,  H05K3/4602 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0113 ,  H05K2203/016 ,  H05K2203/0338

Abstract: In the present invention, a thin film capacitor, having a dielectric layer of a metal oxide having perovskite crystal structure, is formed on a first substrate before the capacitor is transferred onto a second substrate on which an electronic circuit has been formed. Thereafter, patterning of the capacitor and electrical connection are to be carried out.

Abstract translation: 在本发明中，在将电容器转印到其上形成有电子电路的第二基板上之后，在第一基板上形成具有具有钙钛矿晶体结构的金属氧化物的电介质层的薄膜电容器。 此后，将进行电容器的图案化和电连接。