公开(公告)号：US07363706B2

公开(公告)日：2008-04-29

申请号：US11210860

申请日：2005-08-25

Applicant: Eiji Hirata

Inventor： Eiji Hirata

IPC: H01K3/10 ,  H05K1/14 ,  H05K1/11

CPC classification number: H05K3/4652 ,  H05K3/064 ,  H05K3/243 ,  H05K3/421 ,  H05K3/428 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2203/0542 ,  H05K2203/1476 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: This invention provides a multilayer printed wiring board having flat via holes. This is a multilayer printed wiring board formed by alternately laminating multiple metal foils and insulating layers, in which an interlayer connection via pad provided in a first insulating layer, a wiring circuit and an interlayer connection via bottom pad of a second insulating layer are provided in the same surface layer and at least the interlayer connection via pad and the interlayer connection via bottom pad of the second insulating layer have the same thickness.

Abstract translation: 本发明提供一种具有平坦通孔的多层印刷线路板。 这是通过交替层叠多个金属箔和绝缘层而形成的多层印刷布线板，其中通过设置在第一绝缘层中的层间连接通孔焊盘，布线电路和经由第二绝缘层的底焊盘的层间连接设置在 相同的表面层和至少层间连接通孔焊盘和经由第二绝缘层的底部焊盘的层间连接具有相同的厚度。

公开(公告)号：US20080053694A1

公开(公告)日：2008-03-06

申请号：US11850142

申请日：2007-09-05

Applicant: Hong Park ,  Kyoung Lee ,  Hae Jung

Inventor： Hong Park ,  Kyoung Lee ,  Hae Jung

IPC: H05K9/00

CPC classification number: H05K1/0219 ,  H05K2201/09236 ,  H05K2201/09736 ,  H05K2201/09781

Abstract: Provided is a guard trace pattern reducing far-end crosstalk and a printed circuit board having the guard trace pattern. The guard trace pattern includes a first guard trace pattern parallel with two signal lines and a plurality of second guard trace patterns perpendicular to the first guard trace pattern to increase mutual capacitance between the two signal lines and the guard trace pattern and increase mutual capacitance between the two signal lines. The printed circuit board includes the aforementioned guard trace pattern disposed between micro strip transmission lines. A characteristic impedance of the guard trace pattern is different from a characteristic impedance of the micro strip transmission lines, and resistances having the same value as a resistance component value of the characteristic impedance of the guard trace pattern are provided to both ends of the guard trace pattern.

Abstract translation: 提供了减少远端串扰的保护迹线图案和具有保护迹线图案的印刷电路板。 保护迹线图形包括与两条信号线平行的第一保护迹线图形和垂直于第一保护迹线图形的多个第二保护迹线图案，以增加两个信号线和保护迹线图案之间的互电容，并增加两个信号线之间的互电容 两条信号线。 印刷电路板包括设置在微带传输线之间的上述保护迹线图案。 保护迹线图案的特性阻抗与微带传输线的特性阻抗不同，并且具有与保护迹线图案的特性阻抗的电阻分量值相同值的电阻提供给保护迹线的两端 模式。

公开(公告)号：US07327090B2

公开(公告)日：2008-02-05

申请号：US11204123

申请日：2005-08-16

Applicant: Takaaki Hayashi

Inventor： Takaaki Hayashi

IPC: G09G3/10

CPC classification number: H01L27/3276 ,  G02F1/13452 ,  G02F2001/13456 ,  G09G2300/0426 ,  H01L27/3223 ,  H01L2924/0002 ,  H05K1/0265 ,  H05K1/117 ,  H05K3/222 ,  H05K3/361 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/10128 ,  H05K2201/10681 ,  H01L2924/00

Abstract: An electronic module includes an EL section; a first substrate on which the EL section is formed; a second substrate attached to the first substrate; an integrated circuit chip mounted on the second substrate; a plurality of first power supply interconnects formed on the first substrate, extending through a pair of regions located on both sides of the EL section; and a plurality of second power supply interconnects formed on the second substrate, extending through a pair of regions located on both sides of the integrated circuit chip.

Abstract translation: 电子模块包括EL部分; 形成有EL部的第一基板; 附接到所述第一基板的第二基板; 安装在所述第二基板上的集成电路芯片; 多个第一电源互连，形成在第一基板上，延伸穿过位于EL部分两侧的一对区域; 以及多个第二电源互连，形成在第二基板上，延伸穿过位于集成电路芯片两侧的一对区域。

公开(公告)号：US07311240B2

公开(公告)日：2007-12-25

申请号：US10836129

申请日：2004-04-30

Applicant: Kinya Nippa ,  Wei Hong Soh

Inventor： Kinya Nippa ,  Wei Hong Soh

IPC: B23K31/02

CPC classification number: H05K3/363 ,  B23K1/0008 ,  B23K2101/36 ,  B23K2101/42 ,  H05K3/42 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2201/10666 ,  H05K2203/0545

Abstract: Exemplary methods for making a solder joint between two articles are disclosed. The method includes the steps of positioning a first article and a second article to be soldered together. At least one of the first article and the second article has at least one button attached to it. The button has a desired height above a surface of the article to which it is attached. The second article has a quantity of solder located in a position where the solder joint is to be formed. A heat source is applied until the quantity of solder liquefies. The heat source is removed until the solder solidifies with a uniform thickness approximately equal to the height of the button.

Abstract translation: 公开了用于制造两个制品之间的焊接接头的示例性方法。 该方法包括将待焊接在一起的第一制品和第二制品定位的步骤。 第一篇文章和第二篇文章中至少有一篇至少附有一个按钮。 按钮具有与其所附接的物品的表面上方的所需高度。 第二制品具有位于要形成焊点的位置的焊料量。 应用热源直到焊料液化为止。 除去热源，直到焊料以大约等于按钮高度的均匀厚度固化。

公开(公告)号：US07287468B2

公开(公告)日：2007-10-30

申请号：US10908883

申请日：2005-05-31

Applicant: Harry David Cox ,  Hsichang Liu ,  Nike Oluwakemi Medahunsi ,  Krystyna Waleria Semkow

Inventor： Harry David Cox ,  Hsichang Liu ,  Nike Oluwakemi Medahunsi ,  Krystyna Waleria Semkow

IPC: B05C17/06 ,  B32B3/24 ,  B32B15/20

CPC classification number: C25D5/022 ,  C23C28/021 ,  C23C28/023 ,  C25D5/10 ,  H01L21/4867 ,  H05K3/1225 ,  H05K3/245 ,  H05K2201/09736 ,  Y10T428/12063 ,  Y10T428/12361 ,  Y10T428/12486 ,  Y10T428/1291

Abstract: A structure and associated methods of formation. The structure includes a layered configuration comprising a copper layer, a first layer, and a second layer. The copper layer consists essentially of copper. The first and second layers are disposed on opposite sides of the copper layer and are in direct mechanical contact with the copper layer. The first and second layers each consist essentially of a same alloy of nickel and cobalt having a weight percent concentration of cobalt in a range of 3% to 21%. A through hole in the layered configuration extends completely through the first layer, the copper layer, and the second layer, wherein a first opening in the layered configuration extends completely through the first layer and does not extend into any portion of the second layer.

Abstract translation: 一种结构和相关的形成方法。 该结构包括包括铜层，第一层和第二层的分层结构。 铜层基本上由铜组成。 第一层和第二层设置在铜层的相对侧上，并与铜层直接机械接触。 第一层和第二层各自主要由镍和钴的相同合金组成，钴的重量百分比浓度在3％至21％的范围内。 分层结构中的通孔完全延伸穿过第一层，铜层和第二层，其中分层结构中的第一开口完全延伸穿过第一层，并且不延伸到第二层的任何部分。

公开(公告)号：US20070248802A1

公开(公告)日：2007-10-25

申请号：US11574156

申请日：2005-09-30

Applicant: Ryuichi Saito ,  Hiroshi Kagata

Inventor： Ryuichi Saito ,  Hiroshi Kagata

IPC: B32B7/02 ,  C03B29/00

CPC classification number: H05K1/162 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/165 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2203/0113 ,  Y10T428/2495

Abstract: A laminated ceramic component includes a first laminating sheet, a second laminating sheet, a first electrode pattern and a second electrode pattern. The first and the second electrode patterns are located between the first and the second laminating sheets. The second electrode pattern is wider and thinner than the first electrode pattern.

Abstract translation: 层叠陶瓷部件包括第一层压片，第二层压片，第一电极图案和第二电极图案。 第一和第二电极图案位于第一和第二层压片之间。 第二电极图案比第一电极图案更宽和更薄。

公开(公告)号：US20070178766A1

公开(公告)日：2007-08-02

申请号：US11343780

申请日：2006-01-31

Applicant: Gaurab Banerjee ,  Stephen Mooney

Inventor： Gaurab Banerjee ,  Stephen Mooney

IPC: H01R33/00

CPC classification number: H05K1/025 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P5/02 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/044 ,  H05K2201/09736 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: In some embodiments a passive impedance equalization network for high speed serial links is described. The impedance equalization network includes at least one stepped impedance transformer near points of impedance discontinuities. The impedance discontinuities may be at an interface connection between two circuit boards. The impedance discontinuities on a circuit board may be at a die-package interface and/or a package-board interface. The stepped impedance transformer may be formed in a package trace, a board trace or both. Forming the stepped impedance transformers in the traces requires no modification to existing package/board design methodology or technology. The stepped impedance transformers can provide impedance matching over a range of frequencies. To account for modeling errors in the design of the stepped impedance transformers integrated circuits transmitting data over the serial link may include active circuitry to select an output/input impedance for transmitters/receivers. Other embodiments are otherwise disclosed herein.

Abstract translation: 在一些实施例中，描述了用于高速串行链路的无源阻抗均衡网络。 阻抗均衡网络包括阻抗不连续点附近的至少一个阶梯式阻抗变压器。 阻抗不连续性可能在两个电路板之间的接口连接处。 电路板上的阻抗不连续性可能在管芯封装接口和/或封装板接口处。 阶梯式阻抗变压器可以形成为封装迹线，电路板迹线或两者。 在走线中形成阶梯式阻抗变压器不需要修改现有的封装/电路板设计方法或技术。 阶梯式阻抗变压器可以在一定频率范围内提供阻抗匹配。 为了解决在阶梯式阻抗变压器的设计中的建模误差，通过串行链路传输数据的集成电路可能包括用于选择发射机/接收机的输出/输入阻抗的有源电路。 其他实施例在此另外公开。

公开(公告)号：US07230339B2

公开(公告)日：2007-06-12

申请号：US10402101

申请日：2003-03-28

Applicant: Chung C. Key ,  Leong Kum Foo ,  PangToh Tien

Inventor： Chung C. Key ,  Leong Kum Foo ,  PangToh Tien

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/111 ,  H01L23/49816 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/10126 ,  H01L2224/10156 ,  H01L2224/81385 ,  H01L2924/01322 ,  H01L2924/01327 ,  H05K3/3436 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/0369 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A ball grid array device includes a substrate, further including a first major surface and a second major surface. An array of pads is positioned on one of the first major surface or the second major surface. At least some of the pads include a raised ring. The raised ring circumscribes the pad or surrounds an interior pad or land on the substrate.

Abstract translation: 球栅阵列器件包括衬底，还包括第一主表面和第二主表面。 衬垫阵列位于第一主表面或第二主表面之一上。 至少一些垫包括凸起的环。 凸环围绕衬垫或围绕衬垫或衬底上的衬垫。

公开(公告)号：US20070125575A1

公开(公告)日：2007-06-07

申请号：US11634170

申请日：2006-12-06

Applicant: Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

Inventor： Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

IPC: H05K1/00

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09736 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4981 ,  Y10T407/1946 ,  Y10T407/1948 ,  H01L2924/00

Abstract: A dielectric structure comprising: a metal foil; a dielectric layer; and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 μm, the dielectric layer has a thickness of from 0.3 to 5 μm, and the conductor layer has a thickness of from 0.3 to 10 μm, the dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer, and the vias of the dielectric layer have different diameters which are in a range of from 100 to 300 μm, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 μm, and a minimum via pitch is from 100 to 350 μm.

Abstract translation: 一种电介质结构，包括：金属箔; 电介质层; 以及依次设置的导电体层，其中，所述金属箔的厚度为10〜40μm，所述电介质层的厚度为0.3〜5μm，所述导体层的厚度为0.3〜10μm， 电介质结构具有彼此分离并且穿透介电层和导体层两者的多个通孔，并且电介质层的通孔具有不同的直径，其范围为100-300μm，a 导体层的每个通孔的直径大于电介质层的相应通孔的直径为5至50μm，最小通孔间距为100至350μm。

公开(公告)号：US07216424B2

公开(公告)日：2007-05-15

申请号：US11023363

申请日：2004-12-29

Applicant: Ying-Tung Wang

Inventor： Ying-Tung Wang

IPC: H05K3/02 ,  H05K3/06 ,  H05K3/40

CPC classification number: H05K3/3473 ,  B23K35/02 ,  H05K3/0035 ,  H05K3/243 ,  H05K2201/0391 ,  H05K2201/09736 ,  H05K2203/043 ,  H05K2203/0505 ,  H05K2203/054 ,  H05K2203/0723 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49204

Abstract: A method for fabricating electrical connections of a circuit board is provided. The circuit board has a plurality of electrical connection pads thereon. A protective layer is applied on the circuit board and has a plurality of openings for exposing the electrical connection pads. A conductive layer is formed on the protective layer and the electrical connection pads. A resist layer is applied on the conductive layer and has a set of openings for exposing a portion of the conductive layer covering some of the electrical connection pads. A first metal layer is electroplated in the openings of the resist layer. Another set of openings are formed through the resist layer corresponding to the rest of the electrical connection pads. A second metal layer is electroplated on the first metal layer and above the rest of the electrical connection pads to form different electrical connections on the circuit board.

Abstract translation: 提供一种用于制造电路板的电连接的方法。 电路板上有多个电连接焊盘。 保护层被施加在电路板上，并且具有用于暴露电连接焊盘的多个开口。 在保护层和电连接焊盘上形成导电层。 将抗蚀剂层施加在导电层上并具有一组用于暴露覆盖一些电连接焊盘的导电层的一部分的开口。 将第一金属层电镀在抗蚀剂层的开口中。 通过与其余电连接焊盘对应的抗蚀剂层形成另一组开口。 第二金属层电镀在第一金属层上并在电连接焊盘的其余部分上方，以在电路板上形成不同的电连接。