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    Laminate circuit board with selectable connections between wiring layers
    81.
    发明授权
    Laminate circuit board with selectable connections between wiring layers 失效
    层压电路板，布线层之间可选择连接

    公开(公告)号：US5910755A

    公开(公告)日：1999-06-08

    申请号：US959711

    申请日：1997-10-28

    Applicant: Hidehiro Mishiro ,  Kenichiro Tsubone ,  Mitsunori Abe ,  Rie Takada

    Inventor： Hidehiro Mishiro ,  Kenichiro Tsubone ,  Mitsunori Abe ,  Rie Takada

    IPC: H03H7/01 ,  H05K1/00 ,  H05K1/03 ,  H05K1/11 ,  H05K1/16 ,  H03H7/075 ,  H01G4/255

    CPC classification number: H05K1/162 ,  H03H7/0115 ,  H03H7/175 ,  H05K1/0287 ,  H05K1/029 ,  H03H2001/0085 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/165 ,  H05K2201/09309 ,  H05K2201/09945

    Abstract: A laminate capacitor circuit board which permits constants of various kinds of circuit elements to be set by selectively effected connections between wiring layers, and a laminate capacitor circuit board which permits distributed circuit constants in a high-frequency wiring layer sandwiched between two shielding wiring layers to be set as desired. These circuits are formed with at least a pattern of a conductive foil on each dielectric layer, and include a plurality of wiring layers laminated one upon another, a wiring layer for connections laminated to a surface of the plurality of wiring layers laminated one upon another, a plurality of terminal patterns formed on the wiring layer for connections in a state insulated from each other, a plurality of vias for electrically connecting at least two of the plurality of terminal patterns to corresponding ones of the plurality of wiring layers, and connecting means for selectively connecting the plurality of terminal patterns to each other.

    Abstract translation: 通过选择性地实现布线层之间的连接来设置允许各种电路元件的常数的叠层电容器电路板，以及层叠电容器电路板，其允许夹在两个屏蔽布线层之间的高频布线层中的分布电路常数 根据需要设定。 这些电路在每个电介质层上至少形成有导电箔的图案，并且包括彼此层叠的多个布线层，层叠到彼此层叠的多个布线层的表面的用于连接的布线层， 形成在布线层上的多个端子图案，用于在彼此绝缘的状态下连接;多个通孔，用于将多个端子图案中的至少两个电连接到多个布线层中的相应端子;以及连接装置， 选择性地将多个端子图案彼此连接。

    Solder medium for circuit interconnection
    82.
    发明授权
    Solder medium for circuit interconnection 失效
    焊接介质用于电路互连

    公开(公告)号：US5618189A

    公开(公告)日：1997-04-08

    申请号：US588193

    申请日：1996-01-18

    Applicant: Sungho Jin ,  Mark T. McCormack

    Inventor： Sungho Jin ,  Mark T. McCormack

    IPC: B23K35/02 ,  B23K35/14 ,  H05K3/34 ,  H05K3/36 ,  H01R9/09

    CPC classification number: B23K35/0222 ,  H05K3/3436 ,  B23K35/0227 ,  B23K35/0244 ,  H01L2924/0002 ,  H05K2201/0215 ,  H05K2201/083 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2203/0235 ,  H05K2203/0769 ,  H05K2203/104 ,  Y02P70/613

    Abstract: Electronic devices having at least two components with mating contact pads are provided with high-aspect-ratio solder joints between the mating pads. These joints ar formed by placing a composite solder medium containing solder wires in an electrically insulating matrix such that at least two solder wires are in contact with the mating pads, and fusing the wires to the pads. The insulating matrix with remainder of solder wires is then optionally removed from between the said at least two components. The composite solder medium is formed by preparing an elongated body of solder wires in an insulating matrix and cutting off slices of the composite solder medium, the solder wires having a high-aspect-ratio of length to their diameter. Alternatively sheets of the composite solder medium are prepared by magnetically aligning solder coated magnetic particles into columns arranged transverse of an insulating matrix and heating sufficiently to fuse the solder in each column into a continuously conducting solder path.

    Abstract translation: 具有至少两个具有配合接触垫的部件的电子设备在配合焊盘之间设置有高纵横比焊接点。 这些接头通过将包含焊丝的复合焊料介质放置在电绝缘基体中而形成，使得至少两个焊丝与配合焊盘接触，并将焊丝熔合到焊盘。 然后可选地从所述至少两个部件之间移除具有剩余焊丝的绝缘基体。 复合焊料介质通过在绝缘基体中制备细长的焊丝体并且切断复合焊料介质的切片而形成，该焊丝具有与其直径的长宽比的高纵横比。 或者，复合焊料介质的片材通过将焊接涂覆的磁性颗粒磁化地排列成横向于绝缘矩阵布置的列并充分加热以将每个列中的焊料熔合成连续导电的焊接路径来制备。

    Apparatus and method of making laminate an embedded conductive layer
    83.
    发明授权
    Apparatus and method of making laminate an embedded conductive layer 失效
    制造层压板的嵌入式导电层的装置和方法

    公开(公告)号：US5571608A

    公开(公告)日：1996-11-05

    申请号：US523567

    申请日：1995-09-05

    Applicant: N. Deepak Swamy

    Inventor： N. Deepak Swamy

    IPC: H05K1/00 ,  H05K3/42 ,  H05K3/46 ,  B32B9/00

    CPC classification number: H05K3/4641 ,  H05K1/0287 ,  H05K1/0298 ,  H05K2201/068 ,  H05K2201/09309 ,  H05K2201/09718 ,  H05K2201/09945 ,  H05K3/429 ,  Y10T428/24322 ,  Y10T428/24917 ,  Y10T428/249994 ,  Y10T428/2804 ,  Y10T428/31765

    Abstract: An embedded core laminate including a conductive reference plane interposed between two insulation layers, and further interposed between two conductive layers. The assembly is laminated using standard temperature and pressure laminating procedures. Holes for interconnect vias are preferably drilled into the reference plane before laminating. The resulting embedded core laminate has three conductive layers with relatively uniform separation, insuring improved impedance control on each PCB (printed circuit board). Since uniform separation is maintained from one PCB to another, multiple PCBs connected together using embedded core laminates according to the present invention allows minimum cross-talk and characteristic impedance variations from one PCB to the next. The material comprising the conductive layers are preferably chosen with a CTE to match that of semiconductor die to protect solder joints of mounted components from thermal stress, improving reliability of SMT devices and allowing direct chip attach methods to be implemented. Balanced PCBs having five, seven and other odd numbers of conductive layers are available using an embedded core laminate material according to the present invention.

    Abstract translation: 一种嵌入式芯层叠体，其包括介于两个绝缘层之间的导电参考平面，并且还插入在两个导电层之间。 使用标准温度和压力层压程序层压组件。 用于互连通孔的孔优选在层压之前钻入参考平面中。 所得到的嵌入式芯层压板具有三个具有相对均匀分离的导电层，确保了在每个PCB（印刷电路板）上改进的阻抗控制。 由于从一个PCB到另一个PCB保持均匀分离，所以使用根据本发明的嵌入式芯层压板连接在一起的多个PCB允许从一个PCB到下一个PCB的最小串扰和特征阻抗变化。 包括导电层的材料优选地被选择为具有与半导体管芯的CTE匹配的CTE以保护安装的部件的焊点免受热应力，提高SMT器件的可靠性并允许实现直接芯片附接方法。 使用根据本发明的嵌入式芯层压材料可获得具有五个，七个等奇数导电层的平衡PCB。

    Core for electrical connecting substrates and electrical connecting substrates with core, as well as process for the production thereof
    84.
    发明授权
    Core for electrical connecting substrates and electrical connecting substrates with core, as well as process for the production thereof 失效
    用于电连接基板和具有芯的电连接基板的芯，以及用于其生产的工艺

    公开(公告)号：US5442143A

    公开(公告)日：1995-08-15

    申请号：US216717

    申请日：1994-03-23

    Applicant: Walter Schmidt ,  Marco Martinelli

    Inventor： Walter Schmidt ,  Marco Martinelli

    IPC: B32B37/00 ,  B32B7/00 ,  H01L21/00 ,  H01R9/00 ,  H05K1/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/40 ,  H05K3/46

    CPC classification number: H05K3/4038 ,  H05K1/0287 ,  H05K3/06 ,  H05K3/4602 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/068 ,  H05K2203/1476 ,  H05K3/0041 ,  H05K3/4652

    Abstract: The inventive core for electrical connecting substrates, particularly for printed circuit boards and foil circuit boards, has an inner layer (I) with a columnar structure and on either side, metallic cover layers (A,A'), the columnar structure of the inner layer (I) comprising columns (9.1,9.2), which are regularly arranged, spaced from one another and from the cover layers (A,A'), being directed transversely to the service extension of the core and made from an electrically conductive material in a matrix (6) of an electrically insulating material. The cover layers (A,A') e.g. have electrical terminals (16,16', 17,17') in the form of through-plated blind holes (13,14) on selected columns (9) of the inner layer (I) and are structured in such a way that they have a regular pattern of terminals (16,16') on the facing cover layer and terminals (17,17') on the through-connections insulated from the cover layers, this grid pattern can have a size of approximately 0.5 mm.

    Abstract translation: 用于电连接基板的本发明的芯，特别是用于印刷电路板和箔电路板的芯具有具有柱状结构的内层（I），并且在任一侧上具有金属覆盖层（A，A'），内层的柱状结构 包括彼此间隔开并且与覆盖层（A，A'）间隔开的规则排列的柱（9.1,9.2）的层（I）横向于芯的使用延伸部并且由导电材料制成 在电绝缘材料的矩阵（6）中。 覆盖层（A，A'）例如 具有在内层（I）的选定列（9）上的通电镀盲孔（13,14）形式的电端子（16,16'，17,17'），并且以这样的方式构造： 在面层的覆盖层上具有规则的端子（16,16'）图案和与覆盖层绝缘的通孔上的端子（17,17'），该网格图案可以具有大约0.5mm的尺寸。

    Ceramic wiring board and its production
    87.
    发明授权
    Ceramic wiring board and its production 失效
    陶瓷接线板及其生产

    公开(公告)号：US4792646A

    公开(公告)日：1988-12-20

    申请号：US97452

    申请日：1987-09-16

    Applicant: Eyo Enomoto

    Inventor： Eyo Enomoto

    IPC: H05K3/46 ,  H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42

    CPC classification number: H05K1/0306 ,  H05K1/0287 ,  H05K3/0055 ,  H05K2201/09581 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2203/1394 ,  H05K3/181 ,  H05K3/386 ,  H05K3/426 ,  H05K3/429 ,  Y10T29/49163 ,  Y10T29/49165

    Abstract: A ceramic substrate having a plurality of holes arranged regularly with a specified pitch can be used for an universal high density ceramic wiring board, wherein predetermined one or more holes among said plurality of holes are used as through holes for interconnecting both side circuits, and the remaining holes not used for a circuit are filled with an electrical insulating material.Said ceramic substrate of universal type can easily be produced inexpensively and within a short lead time, because said substrate requires no individual mold for each of various circuits to punch a green sheet and can be kept in stock as a fired ceramic substrate.

    Abstract translation: 具有以规定间距规则排列的多个孔的陶瓷基板可以用于通用高密度陶瓷布线板，其中所述多个孔中的预定的一个或多个孔用作用于互连两侧电路的通孔，并且 不用于电路的剩余孔填充有电绝缘材料。 所述通用型陶瓷基板可以容易地廉价地生产并且在短的提前期内，因为所述基板不需要各种电路的单独模具来冲压生片，并且可以作为烧制的陶瓷基板保存。

    Adhesive electrical interconnecting means
    88.
    发明授权
    Adhesive electrical interconnecting means 失效
    胶粘电气互连装置

    公开(公告)号：US4642421A

    公开(公告)日：1987-02-10

    申请号：US770025

    申请日：1985-08-27

    Applicant: Ronald A. Dery ,  Warren C. Jones

    Inventor： Ronald A. Dery ,  Warren C. Jones

    IPC: H01R4/04 ,  H05K1/18 ,  H05K3/30 ,  H05K3/32 ,  H05K3/36 ,  H01B7/08 ,  H01R3/00 ,  H01R43/00 ,  H02G15/08

    CPC classification number: H01R4/04 ,  H05K3/323 ,  H01R23/66 ,  H05K1/181 ,  H05K2201/09945 ,  H05K2201/10727 ,  H05K2201/10977 ,  H05K2203/1189 ,  H05K3/305 ,  H05K3/361

    Abstract: An adhesive interconnecting means is comprised of one or more conductors on an insulating substrate, a first adhesive layer, said first layer being anisotropically conductive and disposed over said conductors and substrate and a second adhesive layer said second layer being a flowable adhesive that extends over the first substrate and anisotropically conductive layer. The anisotropically conductive adhesive is comprised of a nonhomogenous mixture of conductive particles in a nonconductive adhesive binder; the conductive particles, of random size and shape, are dispersed randomly throughout the mixture in noncontiguous conductive units, each unit being comprised of one or more individual particles, the units being sufficiently spaced apart to preclude electrical conductivity between adjacent conductive areas on the same substrate. The flowable adhesive extends over the surface of the first substrate and conductive units to provide insulation whereby upon positioning the first substrate conductors in an overlapping conducting relationship to the second substrate conductors and applying pressure to the positioned areas, the adhesive flows from the positioned areas and exposes the conductive units thus bringing the exposed units into contact and electrical interconnection with the second substrate conductors accompanied by the adhesion of the remaining first substrate surface of the surface of the second substrate.

    Abstract translation: 粘合剂互连装置包括绝缘基底上的一个或多个导体，第一粘合剂层，所述第一层各向异性导电并设置在所述导体和基底上，第二粘合剂层，所述第二层是可流动的粘合剂， 第一基片和各向异性导电层。 各向异性导电粘合剂由非导电粘合剂粘合剂中的导电颗粒的非均匀混合物组成; 随机尺寸和形状的导电颗粒随机地分散在不连续导电单元中的整个混合物中，每个单元由一个或多个单独的颗粒组成，这些单元被充分间隔开以排除相同基底上的相邻导电区域之间的导电性 。 可流动粘合剂在第一基板和导电单元的表面上延伸以提供绝缘，由此在将第一基板导体以与第二基板导体重叠的导电关系定位并向定位区施加压力时，粘合剂从定位的区域流出， 暴露导电单元，从而使暴露的单元与第二基板导体接触并与第二基板的表面的剩余第一基板表面的粘合相配合。

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