中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.016 seconds)

    Sublithographic fuses using a phase shift mask
    1.
    发明授权
    Sublithographic fuses using a phase shift mask 失效
    使用相移掩模的亚光刻保险丝

    公开(公告)号：US6278171B2

    公开(公告)日：2001-08-21

    申请号：US73466800

    申请日：2000-12-13

    Applicant: IBM

    Inventor： ARNDT KENNETH C ,  HSU LOUIS L ,  MANDELMAN JACK A ,  MULLER K PAUL

    IPC: H01L23/525 ,  H01L29/00

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

    Abstract: A method for forming an interconnect wiring structure, such as a fuse structure, comprises forming an opening in an insulating layer using a phase shift mask (the opening having vertical sidewalls sloped sidewalls and horizontal surfaces), depositing a conductive material in the opening and removing the conductive material from the sloped sidewalls and horizontal surfaces, wherein the conductive material remains on the vertical sidewalls as fuse links.

    Abstract translation: 用于形成诸如熔丝结构的互连布线结构的方法包括使用相移掩模（具有垂直侧壁倾斜的侧壁和水平表面的开口）在绝缘层中形成开口，在开口中沉积导电材料并除去 来自倾斜侧壁和水平表面的导电材料，其中导电材料作为熔丝链保持在垂直侧壁上。

    SEMICONDUCTOR STRUCTURE CONTAINING CONDUCTIVE FUSE AND ITS MANUFACTURE
    2.
    发明专利
    SEMICONDUCTOR STRUCTURE CONTAINING CONDUCTIVE FUSE AND ITS MANUFACTURE 失效

    公开(公告)号：JP2000058655A

    公开(公告)日：2000-02-25

    申请号：JP17440199

    申请日：1999-06-21

    Applicant: IBM

    Inventor： ARNDT KENNETH C ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  NARAYAN CHANDRASEKHAR ,  SCHNABEL RAINER F ,  SCHUTZ RONALD J ,  TOEBBEN DIRK

    IPC: H01L21/82 ,  H01L21/768 ,  H01L23/525

    Abstract: PROBLEM TO BE SOLVED: To improve the control of thickness of an insulator layer on a fuse structure, by a method wherein a dielectric structure is positioned on a conduction level, and electric connection is performed at a selected position of the conduction level through the dielectric structure. SOLUTION: On a semiconductor substrate 10 an electric conduction level 1 is formed by using conductive material selected out of aluminum, copper, aluminum copper alloy, and doped polysilicon having metal type conductivity. A dielectric etching stop material layer 2 is stuck on the upper surface of the electric conduction level 1. Electric connection is performed to a selected position of the electric conduction level 1 through the dielectric etching stop material layer 2, and a conductive fuse 21 is constituted. As a result control of the thickness of an insulator layer on the fuse structure containing a self-aligned isolation cap can be improved.

    Method of reducing stress within metallic cover of integrated circuit, and integrated circuit produced using the method
    4.
    发明专利
    Method of reducing stress within metallic cover of integrated circuit, and integrated circuit produced using the method 审中-公开
    集成电路金属外壳中应力减小的方法和使用该方法生产的集成电路

    公开(公告)号：JPH11274158A

    公开(公告)日：1999-10-08

    申请号：JP4899

    申请日：1999-01-04

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

    Inventor： ARNDT KENNETH C ,  CONTI RICHARD A ,  DOBUZINSKY DAVID M ,  ECONOMIKOS LAERTIS ,  GAMBINO JEFFREY P ,  HOH PETER D ,  NARAYAN CHANDRASEKHAR

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768

    CPC classification number: H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    Abstract: PROBLEM TO BE SOLVED: To check cracks within a final passivation laver 13 of an integrated circuit by reducing the stresses within a peripheral dielectric which are due to acute corner of a circuit pattern.
    SOLUTION: Stresses generally induced inside a dielectric is reduced by formings 15 and 17, at lower corner 14" of a circuit pattern 11 before adhering an outer layer (that is, a passivation layer) 13. When patterning it by metallic RIE process, this kind of rounding of the corner is achieved by a two-step metallic etching process, including the first step of creating a vertical sidewall and the second step of tapering the lower part of the vertical sidewall or creating a tapered spacer 15 along the under section of the vertical sidewall. When patterning it by a die machine process, this kind of rounding of the corner is achieved by a two-step trench etching process, including a first step of creating a vertical sidewall and a second step of creating a tapered side wall along the under section of the vertical sidewall.
    COPYRIGHT: (C)1999,JPO

    Abstract translation: 要解决的问题：通过减少外围电介质中由于电路图案的急剧拐角引起的应力来检查集成电路的最终钝化层13内的裂纹。 解决方案：在粘附外层（即钝化层）13之前的电路图案11的下角14“处，通过结构15和17减小电介质内部的应力。当通过金属RIE工艺对其进行图案化时， 通过两步金属蚀刻工艺实现角部的圆角化，包括形成垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤或者沿着垂直侧壁的下部形成锥形间隔件15 垂直侧壁，当通过模具机加工对其进行图案化时，通过两步沟槽蚀刻工艺实现角部圆化，包括形成垂直侧壁的第一步骤和产生锥形侧壁的第二步骤 沿着垂直侧壁的下部。

Patent Agency Ranking