公开(公告)号：EP1889194A4

公开(公告)日：2008-10-01

申请号：EP06760106

申请日：2006-05-18

Applicant: IBM

Inventor： BUEHLER MARKUS T ,  COHN JOHN M ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068

Abstract: Disclosed is a method and system for inserting redundant paths (40,50) into an integrated circuit. Particularly, the invention provides a method for identifying a single via (30) in a first path (40) connecting two elements, determining if an alternate route is available for connecting the two elements (10,20) (other than a redundant via (54)), and for inserting a second path (50)into the available alternate route (70). The combination of the first (40) and second paths (50) provides greater redundancy than inserting a redundant via (54) alone. More importantly, such redundant paths (50) provide for redundancy when congestion prevents a redundant via (54) from being inserted adjacent to the single via (30). An embodiment of the method further comprises removing the single via (30) and any redundant wire segments (51), if all of the additional vias (52) used to form the second path can be made redundant.

Abstract translation: 公开了一种用于将冗余路径（40,50）插入到集成电路中的方法和系统。 特别地，本发明提供了一种用于识别连接两个元件的第一路径（40）中的单个通孔（30）的方法，确定替代路线是否可用于连接两个元件（10,20）（不同于冗余通孔 54）），并且用于将第二路径（50）插入到可用的替代路线（70）中。 第一路径（40）和第二路径（50）的组合提供比单独插入冗余通路（54）更大的冗余。 更重要的是，这种冗余路径（50）在拥塞阻止冗余通路（54）被插入邻近单个通路（30）时提供冗余。 如果可以使用于形成第二路径的所有附加通路（52）变得冗余，则该方法的实施例还包括移除单个通路（30）和任何冗余导线段（51）。

公开(公告)号：EP1644964A4

公开(公告)日：2008-07-30

申请号：EP04778016

申请日：2004-07-09

Applicant: IBM

Inventor： BLANCO RAFAEL ,  COHN JOHN M ,  GOODNOW KENNETH J ,  STOUT DOUGLAS W ,  VENTRONE SEBASTIAN T

IPC: G11C16/04 ,  G06F1/32 ,  G11C5/14 ,  G11C19/08 ,  H01L20060101

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y02D10/171

Abstract: A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

公开(公告)号：AU8760501A

公开(公告)日：2002-01-30

申请号：AU8760501

申请日：2001-07-12

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： ALLEN ARCHIBALD J ,  BULA OREST ,  COHN JOHN M ,  COLE DANIEL ,  CONRAD EDWARD W ,  LEIPOLD WILLIAM C

IPC: H01L21/822 ,  H01L21/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/105 ,  H01L27/12

公开(公告)号：EP1869595A4

公开(公告)日：2009-12-16

申请号：EP05855609

申请日：2005-12-22

Applicant: IBM

Inventor： ADKISSON JAMES W ,  BAZAN GREG ,  COHN JOHN M ,  GRADY MATTHEW S ,  SOPCHAK THOMAS G ,  VALLETT DAVID P

IPC: G06F17/50 ,  G03F1/00

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1573808A4

公开(公告)日：2009-12-09

申请号：EP02799293

申请日：2002-12-20

Applicant: IBM

Inventor： ALLEN ROBERT J ,  COHN JOHN M ,  HABITZ PETER A ,  LEIPOLD WILLIAM ,  WEMPLE IVAN ,  ZUCHOWSKI PAUL S

IPC: H01L23/48 ,  G06F9/45 ,  G06F13/00 ,  G06F17/50 ,  H01L21/321 ,  H01L23/52 ,  H01L23/528 ,  H01L23/535 ,  H01L27/02

CPC classification number: G06F17/5068 ,  H01L21/3212 ,  H01L27/0207

公开(公告)号：WO0207221A3

公开(公告)日：2002-06-13

申请号：PCT/EP0108044

申请日：2001-07-12

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： ALLEN ARCHIBALD J ,  BULA OREST ,  COHN JOHN M ,  COLE DANIEL ,  CONRAD EDWARD W ,  LEIPOLD WILLIAM C

IPC: H01L21/822 ,  H01L21/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/105 ,  H01L27/12 ,  H01L27/02

CPC classification number: H01L27/105 ,  H01L27/0629 ,  H01L28/60

Abstract: A structure for a semiconductor chip which includes a first region having first cells for storing and processing data, and a second region outside the first region having OPC structures, wherein the OPC structures comprise decoupling capacitors. The line widths of the active gates of first cells are the same size or similar in size as the OPC structures. The OPC structures reduce proximity effects of active devices in the first cells, and comprise N-type FETs and P-type FETs, that are located in the second region. The OPC structures may have a width greater than the first cells. The second region can be multiple OPC structures, whereby the second region comprises multiple decoupling capacitors. The active devices in the first cells are separated by a first distance and the OPC structures are separated from the active devices by the first distance.

Abstract translation: 一种用于半导体芯片的结构，包括具有用于存储和处理数据的第一单元的第一区域和具有OPC结构的第一区域外部的第二区域，其中所述OPC结构包括去耦电容器。 第一单元的有源栅极的线宽与OPC结构具有相同的尺寸或相似的尺寸。 OPC结构减少了第一单元中的有源器件的邻近效应，并且包括位于第二区域中的N型FET和P型FET。 OPC结构可以具有比第一单元更大的宽度。 第二区域可以是多个OPC结构，由此第二区域包括多个去耦电容器。 第一单元中的有源器件以第一距离分开，并且OPC结构与有源器件分开第一距离。

公开(公告)号：JP2003076740A

公开(公告)日：2003-03-14

申请号：JP2002136766

申请日：2002-05-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： COHN JOHN M ,  SCOTT W GOULD ,  ROSE RONALD D ,  WEMPLE IVAN L ,  ZUCHOWSKI PAUL S

IPC: G06F17/50 ,  H01L21/82

CPC classification number: G06F17/5022

Abstract: PROBLEM TO BE SOLVED: To provide a high-speed and precise method and a system for analyzing an electric power allocation in an integrated circuit chip.
SOLUTION: The method comprises a step of splitting a clock cycle of the integrated circuit chip into a plurality of periods, a step of splitting the integrated circuit chip into a plurality of cells, a step of performing a static timing analysis to make the plurality of cells to acquire electric wave data by cell and by period and a step of performing the electric power allocation by using the wave data.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供用于分析集成电路芯片中的电力分配的高速精确的方法和系统。 解决方案：该方法包括将集成电路芯片的时钟周期分为多个周期的步骤，将集成电路芯片分割成多个单元的步骤，执行静态时序分析以使多个 小区以及周期以及通过使用波数据执行电力分配的步骤来获取电波数据。

公开(公告)号：WO2006107356A3

公开(公告)日：2007-11-22

申请号：PCT/US2005047083

申请日：2005-12-22

Applicant: IBM ,  ADKISSON JAMES W ,  BAZAN GREG ,  COHN JOHN M ,  GRADY MATTHEW S ,  SOPCHAK THOMAS G ,  VALLETT DAVID P

Inventor： ADKISSON JAMES W ,  BAZAN GREG ,  COHN JOHN M ,  GRADY MATTHEW S ,  SOPCHAK THOMAS G ,  VALLETT DAVID P

IPC: G06F17/50 ,  G03F1/00

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design (300) of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shaped (305) between the adjacent integrated circuit elements based on fill shape rules (310), the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes (320) of a monitor structure (315) in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

Abstract translation: 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）产生集成电路的集成电路设计（300）的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模水平设计的区域，所指定的区域足够大，以便基于填充形状规则（310）在相邻集成电路元件之间放置填充形状（305），填充形状不 为集成电路的运行所需; 以及（c）将监视器结构（315）的一个或多个监视器结构形状（320）放置在所述指定区域中的至少一个中，所述监视器结构不是用于所述集成电路的操作所需要的。

公开(公告)号：WO2006125091A2

公开(公告)日：2006-11-23

申请号：PCT/US2006019257

申请日：2006-05-18

Applicant: IBM ,  BUEHLER MARKUS T ,  COHN JOHN M ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

Inventor： BUEHLER MARKUS T ,  COHN JOHN M ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068

Abstract: Disclosed is a method and system for inserting redundant paths (40,50) into an integrated circuit. Particularly, the invention provides a method for identifying a single via (30) in a first path (40) connecting two elements, determining if an alternate route is available for connecting the two elements (10,20) (other than a redundant via (54)), and for inserting a second path (50)into the available alternate route (70). The combination of the first (40) and second paths (50) provides greater redundancy than inserting a redundant via (54) alone. More importantly, such redundant paths (50) provide for redundancy when congestion prevents a redundant via (54) from being inserted adjacent to the single via (30). An embodiment of the method further comprises removing the single via (30) and any redundant wire segments (51), if all of the additional vias (52) used to form the second path can be made redundant.

Abstract translation: 公开了一种用于将冗余路径（40,50）插入到集成电路中的方法和系统。 特别地，本发明提供一种用于在连接两个元件的第一路径（40）中识别单个通孔（30）的方法，确定替代路径是否可用于连接两个元件（10,20）（除了冗余通孔 54）），并且用于将第二路径（50）插入到可用替代路线（70）中。 第一（40）和第二路径（50）的组合提供比单独插入冗余通路（54）更大的冗余。 更重要的是，当拥塞阻止冗余通路（54）相邻于单通道（30）插入时，这种冗余路径（50）提供冗余。 如果用于形成第二路径的所有附加通孔（52）可以是冗余的，则该方法的实施例还包括移除单个通孔（30）和任何冗余线段（51）。

公开(公告)号：JP2006059348A

公开(公告)日：2006-03-02

申请号：JP2005233945

申请日：2005-08-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COHN JOHN M ,  CULP JAMES A ,  FINKLER ULRICH A ,  HENG FOOK-LUEN ,  MARK A RABIN ,  LEE JIN FUW ,  LAAS W LIEBMANN ,  NORTHROP GREGORY A ,  SEONG NAKGEUON ,  SINGH RAMA N ,  STOK LEON ,  WOLTGENS PIETER J

IPC: G06F17/50 ,  G03F1/08 ,  H01L21/82

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5072

Abstract: PROBLEM TO BE SOLVED: To provide a design tool which improves manufacturability of a design, namely, gives such a design that a fabricated wafer more exactly meets intended/assumed/modeled properties, at lower manufacturing cost and risk. SOLUTION: A design system for designing complex integrated circuits (ICs), a method of IC design, and program products therefor are provided. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data preparatory unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种提高设计的可制造性的设计工具，即提供这样的设计，即制造的晶片更准确地满足预期/假设/建模性能，具有较低的制造成本和风险。

解决方案：提供了一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法及其程序产品。 布局单元接收表示网格和字形格式的部分的电路描述。 检查单元检查设计的网格和字形部分。 精心设计单元从检查的设计生成目标布局。 数据准备单元准备面具制作的目标布局。 模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。 版权所有（C）2006，JPO＆NCIPI