公开(公告)号：JP2004088089A

公开(公告)日：2004-03-18

申请号：JP2003184250

申请日：2003-06-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BROWN JEFFREY S ,  FRIED DAVID M ,  EDWARD J NOWACK ,  RAINEY BETH ANN

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/108 ,  H01L27/10873 ,  H01L28/90 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a 2-device type DRAM cell which has high soft error resistance that is one of trouble mechanisms of a DRAM, and which is simply manufactured. SOLUTION: The DRAM cell is a memory cell (two-device type DRAM) including first and second transfer devices in a completely deplete state each including one body(semiconductor rail), and first and second diffusion electrodes. The DRAM cell further includes a difference storage capacitor which has at least one node that is adjacent to the first and the second diffusion electrodes of each transfer device, and is electrically connected with the same. The difference storage capacitor includes a main capacitor and a plurality of specific capacitors, and the main capacitor has electrostatic capacitance at least 5 times larger than that of the plurality of the specific capacitors. COPYRIGHT: (C)2004,JPO

公开(公告)号：JPH10321807A

公开(公告)日：1998-12-04

申请号：JP12094798

申请日：1998-04-30

Applicant: IBM

Inventor： FEI D BAKER ,  JEFFREY S BROWN ,  ROBERT J GAUZAR ,  STEPHEN J HORMES ,  ROBERT K LADY ,  EDWARD J NOWACK ,  VOLDMAN STEVEN H

IPC: H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To improve the latch-up resistance of a CMOS device by forming implants on the edges of an N well and/or a P well by using a hybrid resist and, at the same time, to improve the device density of the CMOS device by promoting the scaling of the device. SOLUTION: A wafer section 2100 can be completed by an appropriate manufacturing method, for example, by forming a device gate, a contact diffusion area, etc. In the wafer section 2100, in addition, N and P contact diffusion areas are formed. In these contact diffusion areas, implants are usually formed on the surface of silicon which is not masked with a polysilicon gate. Therefore, a method and a structure for reducing the latch-up of a CMOS device by forming N and/or P edge implants on the edges of a P-well, N-well, and/or a double well are obtained.

公开(公告)号：JP2000101093A

公开(公告)日：2000-04-07

申请号：JP24211799

申请日：1999-08-27

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  EDWARD J NOWACK ,  WILBUR D PRISER ,  MIN H TONG

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a device structure of SOI(silicon on isulator) CMOS (complementary metal oxide semiconductor) in which avalanche multiplication of current flowing through a device is increased when an FET(field effect transistor) is turned on and body charges are removed when the FET is turned off. SOLUTION: An FET having an electric floating body is substantially isolated electrically from a substrate. A high resistance path 16 for coupling the floating body is provided at the source. The resistor is operated as a floating body for active switching and a body grounded in waiting mode in order to reduce leakage current. The high resistance path has a resistance of at least 1 MΩ and made of polysilicon. The resistor is formed using a split polysilicon process for opening a hole in a first polysilicon layer in order that an embedded contact mask 19 brings a second polysilicon layer into contact with the substrate.

公开(公告)号：JPH11289016A

公开(公告)日：1999-10-19

申请号：JP2366499

申请日：1999-02-01

Applicant: IBM

Inventor： EDWARD J NOWACK ,  RONALD D ROSSI ,  MIN H TONG

IPC: H01L29/78 ,  G11C19/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/115 ,  H01L29/772

Abstract: PROBLEM TO BE SOLVED: To provide a DTFET(dynamic threshold field effect transistor) which can improve a switching speed in a transistor circuit and can use a power voltage higher than 0.5 volts. SOLUTION: A DTFET 12 includes a resistance 18 connected between an input node 14 and a body 15. Inclusion of such a resistance can realization of the DTFET by a bulk technique and can utilize a power voltage higher than 0.5 volts. The resistance 18 can be provided in the form of a resistance integrated within a transistor or in the form of an independent element separated from the transistor.

公开(公告)号：JP2010153788A

公开(公告)日：2010-07-08

申请号：JP2009229804

申请日：2009-10-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDWARD J NOWACK ,  SLINKMAN JAMES ALBERT ,  BOTULA ALAN BERNARD

IPC: H01L29/786 ,  H01L21/3205 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/52 ,  H01L27/04 ,  H01L27/08 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L21/84 ,  H01L21/76224 ,  H01L21/76251 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit which is reduced in capacitive coupling of a semiconductor-on-insulator (SOI) substrate.
SOLUTION: First doped semiconductor regions 18 having the same conductivity type dopant as a bottom semiconductor layer and second doped semiconductor regions 28 having an opposite conductivity type dopant are formed directly underneath a buried insulator layer 20 of the (SOI) substrate. The first doped semiconductor regions 18 and the second doped semiconductor regions 28 are electrically grounded or forward-biased relative to the bottom semiconductor layer at a voltage that is insufficient to cause excessive current due to forward-biased injection of minority carriers into the bottom semiconductor layer, i.e., at a potential difference not exceeding 0.6V to 0.8V. The electrical charges formed in an induced charge layer by the electrical signal in semiconductor devices on the top semiconductor layer are drawn through electrical contacts connected to the first and the second doped semiconductor regions, thereby reducing harmonic signals in the semiconductor devices.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供减小绝缘体上半导体（SOI）衬底的电容耦合的集成电路。 解决方案：具有与半导体层相同的导电类型掺杂剂的第一掺杂半导体区域18和具有相反导电型掺杂剂的第二掺杂半导体区域28直接形成在（SOI）衬底的掩埋绝缘体层20的下方。 第一掺杂半导体区域18和第二掺杂半导体区域28相对于底部半导体层以不足以引起由于少数载流子正向偏置注入底部半导体层而导致过大电流的电压而被电接地或正向偏置 即电位差不超过0.6V至0.8V。 通过在顶部半导体层上的半导体器件中的电信号在感应电荷层中形成的电荷通过连接到第一和第二掺杂半导体区域的电触点而被拉出，从而减少半导体器件中的谐波信号。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2002314094A

公开(公告)日：2002-10-25

申请号：JP2002052160

申请日：2002-02-27

Applicant: IBM

Inventor： BRYANT ANDRES ,  LASKY JEROME B ,  EDWARD J NOWACK ,  RANKIN JED H ,  MIN H TON

IPC: H01L29/43 ,  H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/08 ,  H01L27/11 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for avoiding a floating body effect in an SOI structure. SOLUTION: A semiconductor device includes SOI FETs which include silicon bodies on an insulating layer on a conductive substrate. Gate dielectrics and gates are formed on the surfaces of the silicon bodies, and sources and drains are formed on two sides of the gates. Buried body contacts to substrate conductors are formed under the third side of the gate. The buried body contacts do not extend to the upper face of the silicon bodies. The buried body contacts are separated from the gates by second dielectrics whose thicknesses are generally larger than the thicknesses of the first gate dielectrics. The buried body contacts are plugs made of conductive materials, and the second dielectrics cover the body contacts under the gates. The FETs can be used in a SRAM circuit or any other type of circuit having the silicon on insulator(SOI) structure.

公开(公告)号：JPH11317499A

公开(公告)日：1999-11-16

申请号：JP890299

申请日：1999-01-18

Applicant: IBM

Inventor： EDWARD J NOWACK ,  SHAO WEI TAN ,  MIN H TON

IPC: H01L27/04 ,  H01L21/329 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To achieve a semiconductor with an improved embedded resistor and an embedder capacitor by arranging a polysilicon gate on the region of a resistance element and arranging a separation layer between the polysilicon gate and the resistance element. SOLUTION: A semiconductor device includes a substrate, a characteristic polysilicon gate 58, a resistance element, and a separation layer. The polysilicon gate 58 is arranged on the region of the resistance element, and the separation layer is arranged between the polysilicon gate 58 and the resistance element. Also, an embedded resistor 52 is an N-type dope and is provided with a P well 64. The diffusion resistor 52 is an N-type doping. Input 54 and output 56 are in electrical contact. An N-type source doping/drain doping 60 is located at the lower side of the region of the input 54 and the output 56. Since the P well in placed away from the lower portion of the diffusion resistor 52, parasitic junction capacitance is low. Therefore, the execution is simple, so that the change costs of a device does not become too high.