公开(公告)号：KR20100123596A

公开(公告)日：2010-11-24

申请号：KR20100030429

申请日：2010-04-02

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  IYER SUBRAMANIAN S

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L24/94 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/16 ,  H01L24/28 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80801 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83201 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: PURPOSE: A 3D integration structure and method using bonded metal planes are provided to connect metal layers through metal to metal. CONSTITUTION: A second semiconductor structure(20) comprises a semiconductor wafer having devices(23), a BEOL wiring(24), an insulating layer(26), oxide, and a metal layer(28). The second semiconductor structure is similar to that of the first semiconductor structure(10). The first and second semiconductor structure have different functions while a metal layer having holes.

Abstract translation: 目的：提供使用接合金属平面的3D集成结构和方法，以通过金属与金属连接金属层。 构成：第二半导体结构（20）包括具有器件（23），BEOL布线（24），绝缘层（26），氧化物和金属层（28）的半导体晶片。 第二半导体结构与第一半导体结构（10）类似。 第一和第二半导体结构具有不同的功能，而具有孔的金属层。

公开(公告)号：EP2596526A4

公开(公告)日：2015-01-28

申请号：EP11810162

申请日：2011-07-12

Applicant: IBM ,  IBM

Inventor： FAROOQ MUKTA G ,  HANNON ROBERT ,  VOLANT RICHARD P

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81801 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

公开(公告)号：EP2084738A4

公开(公告)日：2011-10-12

申请号：EP07844133

申请日：2007-10-11

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  YANG HAINING S ,  WONG KEITH KWONG HON ,  FAROOQ MUKTA G

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2095419A4

公开(公告)日：2011-03-16

申请号：EP07865500

申请日：2007-12-11

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  JUNG DAE-YOUNG ,  MELVILLE IAN D

IPC: H01L21/78 ,  H01L21/00 ,  H01L23/00 ,  H01L29/06

CPC classification number: H01L21/67092 ,  H01L21/78 ,  H01L23/562 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2422366A4

公开(公告)日：2014-01-22

申请号：EP10767507

申请日：2010-04-08

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R

IPC: H01L21/98 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L24/06 ,  H01L24/80 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/80896 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00

Abstract: A method of implementing three-dimensional (3D) integration of multiple integrated circuit (IC) devices includes forming a first insulating layer over a first IC device; forming a second insulating layer over a second IC device; forming a 3D, bonded IC device by aligning and bonding the first insulating layer to the second insulating layer so as to define a bonding interface therebetween, defining a first set of vias within the 3D bonded IC device, the first set of vias landing on conductive pads located within the first IC device, and defining a second set of vias within the 3D bonded IC device, the second set of vias landing on conductive pads located within the second device, such that the second set of vias passes through the bonding interface; and filling the first and second sets of vias with a conductive material.

公开(公告)号：EP2313923A4

公开(公告)日：2013-02-20

申请号：EP09808777

申请日：2009-08-19

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KOESTER STEVEN J ,  PORUSHOTHAMAN SAMPATH ,  YU ROY R

IPC: H01L27/06 ,  H01L27/105

CPC classification number: H01L27/105 ,  H01L24/11 ,  H01L27/0688 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

公开(公告)号：EP2008301A4

公开(公告)日：2012-09-05

申请号：EP07760071

申请日：2007-04-04

Applicant: IBM

Inventor： EDELSTEIN DANIEL C ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  MELVILLE IAN D

IPC: H01L21/44 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03019 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/13116 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/01074 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01039 ,  H01L2224/05552

公开(公告)号：JP2004188497A

公开(公告)日：2004-07-08

申请号：JP2003389972

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FAROOQ MUKTA G ,  INTERRANTE MARIO J ,  SABLINSKI WILLIAM E

IPC: B23K35/26 ,  C22C13/00 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H05K3/28 ,  H05K3/34

CPC classification number: H01L21/6835 ,  B23K35/262 ,  B23K2201/40 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81024 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3463 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a lead-free hierarchical structure for packaging electronic circuits.
SOLUTION: The electronic circuit package has the hierarchy of liquidus temperature in mutual joining of solder limiting fused degree of the mutually joining of the solder with a C4 (current controlled collapse chip joining) technique between the following second level joining /assembling-treatment and a rework-treatment. The solder hierarchy is used to Sn/Ag and Sn/Cu non-eutectic solder alloy having high liquidus temperature for mutually joining of the solder with the C4 technique at the first level and used to an alloy having low liquidus temperature for mutually joining the second level. When the joining/assembling treatment of a chip-carrier into a PCB is performed, the mutually joining part with the C4 technique is not fully fused. These continuously keep liquid having smaller amount than that of a fully fused alloy. This reduces the expansion of solder joining and as this result the stress is weakened in the mutually joining with the C4 technique.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2006059814A

公开(公告)日：2006-03-02

申请号：JP2005238111

申请日：2005-08-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BERNIER WILLIAM E ,  CHENG TIEN-JEN ,  COLE MARIE S ,  EICHSTADT DAVID E ,  FAROOQ MUKTA G ,  PHIZHIMONS JOHN A ,  LEWIS S GOLDMAN ,  KNICKERBOCKER JOHN U ,  LOPEZ TASHA E ,  WELSH DAVID J

IPC: H01R11/01

CPC classification number: H01L21/563 ,  H01L23/3171 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13566 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01R43/0256 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To provide a connector surrounded with a compressive material which connects a device with a support without separation.
SOLUTION: An unleaded connector is formed on the device, the unleaded connector is surrounded with a compressive film, the device is combined with the support, i.e. the unleaded connector connects the device with the support electrically, and a clearance between the support and the device is filled with an insulation underfill. A device supporting structure constituted of these and a forming method for it are disclosed.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种被压缩材料包围的连接器，该压缩材料将装置与支撑件连接而不分离。 解决方案：在设备上形成无铅连接器，无铅连接器被压缩膜包围，该装置与支撑件组合，即，无铅连接器将该装置与支撑件电连接，支撑件之间的间隙 并且该装置填充有绝缘底部填充物。 公开了一种由它们构成的装置支撑结构及其形成方法。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2010157704A

公开(公告)日：2010-07-15

申请号：JP2009271765

申请日：2009-11-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GAMBINO JEFFREY P ,  PETRARCA KEVIN S ,  FAROOQ MUKTA G ,  RAMACHANDRA DEIBAKARUNI

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/866

CPC classification number: H01L28/60 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a metal-insulator-metal capacitor having improved manufacturing possibility, and to provide a method for fabricating the same. SOLUTION: A semiconductor structure including the vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供具有改进的制造可能性的金属 - 绝缘体 - 金属电容器，并提供其制造方法。 解决方案：包括垂直金属 - 绝缘体 - 金属电容器的半导体结构以及包括垂直金属 - 绝缘体 - 金属电容器的半导体结构的制造方法，每个都使用来自虚设金属氧化物半导体场效应晶体管的结构部件 并且形成在位于半导体衬底上方的隔离区域上。 虚拟金属氧化物场效应晶体管可以与位于包括隔离区域的半导体衬底之上的金属氧化物半导体场效应晶体管同时形成。 金属 - 绝缘体 - 金属电容器使用栅极作为电容器板，均匀厚度的栅极间隔物作为栅极电介质和作为另一个电容器板的接触通孔。 均匀厚度的栅极间隔物可以包括用于增强电容的导体层。 使用单个接触通孔的镜像金属 - 绝缘体 - 金属电容器结构也可用于增强电容。 版权所有（C）2010，JPO＆INPIT