Patent search ap:("IBM" OR "IBM") AND inv:"FAROOQ MUKTA G" Page 1

1.

发明公开
3d integration structure and method using bonded metal planes 无效
Title translation: 3D集成结构和使用绑定金属平面的方法

公开(公告)号：KR20100123596A

公开(公告)日：2010-11-24

申请号：KR20100030429

申请日：2010-04-02

Applicant: IBM

Inventor： FAROOQ MUKTA G , IYER SUBRAMANIAN S

IPC: H01L21/768 , H01L21/28

CPC classification number: H01L24/94 , H01L21/76898 , H01L21/8221 , H01L24/16 , H01L24/28 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2224/13009 , H01L2224/13099 , H01L2224/80345 , H01L2224/80357 , H01L2224/80801 , H01L2224/80895 , H01L2224/80896 , H01L2224/83201 , H01L2224/83801 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105

Abstract: PURPOSE: A 3D integration structure and method using bonded metal planes are provided to connect metal layers through metal to metal. CONSTITUTION: A second semiconductor structure(20) comprises a semiconductor wafer having devices(23), a BEOL wiring(24), an insulating layer(26), oxide, and a metal layer(28). The second semiconductor structure is similar to that of the first semiconductor structure(10). The first and second semiconductor structure have different functions while a metal layer having holes.

Abstract translation: 目的：提供使用接合金属平面的3D集成结构和方法，以通过金属与金属连接金属层。构成：第二半导体结构（20）包括具有器件（23），BEOL布线（24），绝缘层（26），氧化物和金属层（28）的半导体晶片。第二半导体结构与第一半导体结构（10）类似。第一和第二半导体结构具有不同的功能，而具有孔的金属层。

2.

发明公开
METAL-CONTAMINATION -FREE THROUGH-SUBSTRATE VIA STRUCTURE 审中-公开
Title translation: 金属无污染基材贯通结构

公开(公告)号：EP2596526A4

公开(公告)日：2015-01-28

申请号：EP11810162

申请日：2011-07-12

Applicant: IBM , IBM

Inventor： FAROOQ MUKTA G , HANNON ROBERT , VOLANT RICHARD P

IPC: H01L21/768 , H01L23/00 , H01L23/48

CPC classification number: H01L21/76898 , H01L21/568 , H01L21/6835 , H01L23/3171 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/93 , H01L24/94 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/03002 , H01L2224/0401 , H01L2224/0557 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/11002 , H01L2224/11334 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/81801 , H01L2224/93 , H01L2224/94 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/10253 , H01L2924/12044 , H01L2924/15788 , H01L2924/014 , H01L2224/81 , H01L2224/03 , H01L2224/11 , H01L2924/00 , H01L2224/05552

3.

发明公开
ENHANCED INTERCONNECT STRUCTURE 审中-公开
Title translation: 高级的连接结构

公开(公告)号：EP2084738A4

公开(公告)日：2011-10-12

申请号：EP07844133

申请日：2007-10-11

Applicant: IBM

Inventor： YANG CHIH-CHAO , YANG HAINING S , WONG KEITH KWONG HON , FAROOQ MUKTA G

IPC: H01L21/768 , H01L23/532

CPC classification number: H01L23/53238 , H01L21/76834 , H01L21/76843 , H01L21/76883 , H01L21/76885 , H01L23/53223 , H01L23/53266 , H01L2924/0002 , H01L2924/00

4.

发明公开
SEMICONDUCTOR CHIP SHAPE ALTERATION 审中-公开
Title translation: FORM在半导体芯片中的变化

公开(公告)号：EP2095419A4

公开(公告)日：2011-03-16

申请号：EP07865500

申请日：2007-12-11

Applicant: IBM

Inventor： FAROOQ MUKTA G , JUNG DAE-YOUNG , MELVILLE IAN D

IPC: H01L21/78 , H01L21/00 , H01L23/00 , H01L29/06

CPC classification number: H01L21/67092 , H01L21/78 , H01L23/562 , H01L29/0657 , H01L2924/0002 , H01L2924/00

5.

发明公开
THREE DIMENSIONAL INTEGRATED CIRCUIT INTEGRATION USING DIELECTRIC BONDING FIRST AND THROUGH VIA FORMATION LAST 审中-公开
Title translation: 三维集成电路的电介质粘结AS第一步，通过教育作为最后一步安装

公开(公告)号：EP2422366A4

公开(公告)日：2014-01-22

申请号：EP10767507

申请日：2010-04-08

Applicant: IBM

Inventor： FAROOQ MUKTA G , HANNON ROBERT , IYER SUBRAMANIAN S , KINSER EMILY R

IPC: H01L21/98 , H01L21/768 , H01L25/065

CPC classification number: H01L21/76898 , H01L24/06 , H01L24/80 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/06181 , H01L2224/08146 , H01L2224/16145 , H01L2224/32145 , H01L2224/80896 , H01L2224/8385 , H01L2224/9202 , H01L2224/94 , H01L2225/06541 , H01L2924/14 , H01L2924/00014 , H01L2224/83 , H01L2224/80 , H01L2924/00

Abstract: A method of implementing three-dimensional (3D) integration of multiple integrated circuit (IC) devices includes forming a first insulating layer over a first IC device; forming a second insulating layer over a second IC device; forming a 3D, bonded IC device by aligning and bonding the first insulating layer to the second insulating layer so as to define a bonding interface therebetween, defining a first set of vias within the 3D bonded IC device, the first set of vias landing on conductive pads located within the first IC device, and defining a second set of vias within the 3D bonded IC device, the second set of vias landing on conductive pads located within the second device, such that the second set of vias passes through the bonding interface; and filling the first and second sets of vias with a conductive material.

6.

发明公开
3D INTEGRATED CIRCUIT DEVICE FABRICATION 审中-公开
Title translation: 制造器件与集成电路3D

公开(公告)号：EP2313923A4

公开(公告)日：2013-02-20

申请号：EP09808777

申请日：2009-08-19

Applicant: IBM

Inventor： FAROOQ MUKTA G , HANNON ROBERT , IYER SUBRAMANIAN S , KOESTER STEVEN J , PORUSHOTHAMAN SAMPATH , YU ROY R

IPC: H01L27/06 , H01L27/105

CPC classification number: H01L27/105 , H01L24/11 , H01L27/0688 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/0557 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599

Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.