公开(公告)号：EP2596526A4

公开(公告)日：2015-01-28

申请号：EP11810162

申请日：2011-07-12

Applicant: IBM ,  IBM

Inventor： FAROOQ MUKTA G ,  HANNON ROBERT ,  VOLANT RICHARD P

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81801 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

公开(公告)号：EP1461828A4

公开(公告)日：2005-09-28

申请号：EP02803310

申请日：2002-11-07

Applicant: IBM

Inventor： VOLANT RICHARD P ,  BISSON JOHN C ,  COTE DONNA R ,  DALTON TIMOTHY J ,  GROVES ROBERT A ,  PETRARCA KEVIN S ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

IPC: B81B3/00 ,  B81C1/00 ,  H01H49/00 ,  H01H59/00

CPC classification number: B81C1/00246 ,  B81B2201/016 ,  B81B2201/018 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0122 ,  B81C2203/0735 ,  H01G5/40 ,  H01H59/0009

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

公开(公告)号：EP1756862A4

公开(公告)日：2011-03-02

申请号：EP05741890

申请日：2005-04-28

Applicant: IBM

Inventor： CHINTHAKINDI ANIL K ,  GROVES ROBERT A ,  TRETIAKOV YOURI V ,  VAED KUNAL ,  VOLANT RICHARD P

IPC: H01L23/522 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01P11/00

CPC classification number: H01P11/003 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/53238 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

公开(公告)号：EP1602113A4

公开(公告)日：2010-12-29

申请号：EP03781593

申请日：2003-10-28

Applicant: IBM

Inventor： VOLANT RICHARD P ,  FLORKEY JOHN E ,  GROVES ROBERT A

IPC: B81B3/00 ,  H01F7/06 ,  H01F7/14 ,  H01H59/00 ,  H03K17/965 ,  H01F21/04

CPC classification number: H03K17/965 ,  H01F7/066 ,  H01F7/14 ,  H01F2007/068 ,  H01H59/0009

公开(公告)号：EP1366512A4

公开(公告)日：2009-07-08

申请号：EP01987440

申请日：2001-12-19

Applicant: IBM

Inventor： WALKER GEORGE F ,  GOLDBLATT RONALD D ,  GRUBER PETER A ,  HORTON RAYMOND R ,  PETRARCA KEVIN S ,  VOLANT RICHARD P ,  CHENG TIEN-JEN

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485 ,  H01L21/44 ,  H01L23/48

CPC classification number: H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract translation: 描述了用于形成适用于引线键合和焊料凸点倒装芯片连接（例如可控塌陷芯片连接（C4））的公共输入 - 输出（I / O）位置的过程。 本发明特别适用于使用铜作为互连材料的半导体芯片，其中用于制造这种芯片的软电介质容易因结合力而损坏。 本发明通过在衬垫的顶表面上提供具有贵金属的部位，同时提供扩散阻挡层以维持金属互连的高导电性，从而降低了损坏的风险。 通过提供在衬底中形成的特征中选择性地沉积金属层的方法来减少用于在衬底内形成I / O部位的工艺步骤。 由于本发明的I / O站点可以用于引线键合或焊料凸点连接，这为芯片互连选项提供了增加的灵活性，同时还降低了工艺成本。

公开(公告)号：WO2004038916A3

公开(公告)日：2004-08-12

申请号：PCT/EP0312399

申请日：2003-09-18

Applicant: IBM ,  IBM FRANCE

Inventor： CHINTHAKINDI ANIL K ,  GROVES ROBERT A ,  STEIN KENNETH J ,  SUBBANNA SESHADRI ,  VOLANT RICHARD P

IPC: B81B7/00 ,  B81C1/00 ,  H01G5/011 ,  H01G5/18 ,  H03J3/18 ,  B81B3/00 ,  H01G5/16

CPC classification number: H01G5/18 ,  B81B2201/01 ,  H01G5/011 ,  Y10S257/924

Abstract: A three-dimensional micro-electromechanical (MEM) varactor is described wherein a movable beam (50) and fixed electrodes (51) are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the "chip side" while the fixed bottom electrode is fabricated on a separated substrate "carrier side". Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and "flipped over", aligned and joined to the "carrier" substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.

Abstract translation: 描述了三维微机电（MEM）变容二极管，其中可移动光束（50）和固定电极（51）分别制造在彼此耦合的分离的基板上。 具有梳状驱动电极的可移动光束在“芯片侧”上制造，而固定底部电极制造在分离的基板“载体侧”上。 在衬底的两个表面上制造器件时，芯片侧器件被切割并“翻转”，对准并接合到“载体”衬底以形成最终器件。 梳状驱动（鳍）电极用于致动，同时电极的运动提供电容的变化。 由于所涉及的驱动力恒定，可以获得大的电容调谐范围。 该装置的三维方面具有较大的表面积。 当提供大的纵横比特征时，可以使用较低的致动电压。 在制造时，MEMS器件被完全封装，不需要额外的器件封装。 此外，由于可以在晶片规模（晶片级MEMS封装）上进行取向和接合，所以可以以更低的成本获得改进的器件产量。

公开(公告)号：EP1668745A4

公开(公告)日：2008-12-03

申请号：EP03770552

申请日：2003-09-30

Applicant: IBM

Inventor： VOLANT RICHARD P ,  PETRARCA KEVIN S ,  WALKER GEORGE F

IPC: H01R12/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5387 ,  H01L24/18 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/9222 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A three-dimensional package consisting of a plurality of folded integrated circuit chips ( 100, 110, 120 ) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip ( 130 ) is provided with additional interconnect wiring to a substrate ( 500 ), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.

公开(公告)号：EP1535297A4

公开(公告)日：2007-07-18

申请号：EP02768707

申请日：2002-08-26

Applicant: IBM

Inventor： JAHNES CHRISTOPHER V ,  LUND JENNIFER L ,  SAENGER KATHERINE L ,  VOLANT RICHARD P

IPC: B81B3/00 ,  B81C1/00 ,  G02B5/00 ,  G02B26/00 ,  G02B26/08 ,  H01H57/00 ,  H01H59/00

CPC classification number: H01H59/0009 ,  H01H2057/006

Abstract: A micro-electromechanical (MEM) RF switch provided with a deflectable membrane (60) activates a switch contact or plunger (40). The membrane incorporates interdigitated metal electrodes (70) which cause a stress gradient in the membrane when activated by way of a DC electric field. The stress gradient results in a predictable bending or displacement of the membrane (60), and is used to mechanically displace the switch contact (30). An RF gap area (25) located within the cavity (250) is totally segregated from the gaps (71) between the interdigitated metal electrodes (70). The membrane is electrostatically displaced in two opposing directions, thereby aiding to activate and deactivate the switch. The micro-electromechanical switch includes: a cavity (250); at least one conductive path (20) integral to a first surface bordering the cavity; a flexible membrane (60) parallel to the first surface bordering the cavity (250), the flexible membrane (60) having a plurality of actuating electrodes (70); and a plunger (40) attached to the flexible membrane (60) in a direction away from the actuating electrodes (70), the plunger (40) having a conductive surface that makes electric contact with the conductive paths, opening and closing the switch.

公开(公告)号：EP1535296A4

公开(公告)日：2007-04-04

申请号：EP02746591

申请日：2002-06-14

Applicant: IBM

Inventor： DELIGIANNI HARIKLIA ,  GREENBERG DAVID R ,  JAHNES CHRISTOPHER V ,  LUND JENNIFER L ,  SAENGER KATHERINE L ,  VOLANT RICHARD P

IPC: H01H57/00 ,  H01H59/00 ,  H01L21/00

CPC classification number: H01H59/0009

Abstract: A micro-electromechanical switch (MEMS) having a deformable elastomeric element (1) which exhibits a large change in conductivity with a small amount of displacement. The deformable elastomeric element (1) is displaced by an electrostatic force that is applied laterally resulting in a small transverse displacement. The transversal displacement, in turn, pushes a metallic contact (7) against two conductive paths (5, 6), allowing passage of electrical signals. The elastomer (1) is provided on two opposing sids with embedded metallic elements (9, 10), such as impregnated metallic rods, metallic sheets, metallic particles, or conductive paste. Actuation electrodes (18, 8) are placed parallel to the conductive sides of the elastomer. A voltage applied between the conductive side of the elastomer and the respective actuation electrodes (18, 8) generate the electrostatic attractive force that compresses the elastomer (1), creating the transverse displacement that closes the MEMS. The elastomeric based MEMS extends the lifetime of the switch by extending fatigue life of the deformable switch elements.

公开(公告)号：JP2002033395A

公开(公告)日：2002-01-31

申请号：JP2001160150

申请日：2001-05-29

Applicant: IBM

Inventor： GREGORY G FREEMAN ,  ROBERT A GROVES ,  JEFFREY JOHNSON ,  SESHADORI SUBANA ,  VOLANT RICHARD P

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/768 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082

Abstract: PROBLEM TO BE SOLVED: To improve the high-frequency performance of transistor design, and a manufacturing yield by combining processes from various techniques for eliminating and reducing the source of parasitic capacity. SOLUTION: Collector, base, and emitter regions are formed on a substrate, a second substrate is mounted, an original substrate is completely or partially removed, a non-active collector region is removed or is set to a semi-insulator, and wiring and contact are performed from the original back surface of a chip. A dielectric material used in a manufacturing process is removed, thus further reducing electrostatic capacity. A high-frequency transistor is jointed to a CMOS chip or a wafer, thus forming a BICMOS chip.