公开(公告)号：EP1532659A4

公开(公告)日：2005-12-14

申请号：EP03736783

申请日：2003-06-03

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETH ANN ,  SADANA DEVENDRA K

IPC: H01L27/088 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/7851 ,  H01L21/823828 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7853

Abstract: The present invention thus provides a device structure and method for forming fin (210) Field Effect Transistors (FETs) from bulk semiconductor wafers (200) while providing improved wafer to wafer device uniformity. Specifically, the invention provides a height control layer (212), such as a damaged portion of the substrate (200) or a marker layer, which provides uniformity of fin height. Additionally, the invention provides provides isolation (214) between fins (210) which also provides for optimization and narrowing of fin width by selective oxidation of a portion (212) of the substrate relative to an oxidized portion (216) of the fin sidewalk. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

公开(公告)号：WO03001604A2

公开(公告)日：2003-01-03

申请号：PCT/EP0206202

申请日：2002-06-06

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： BRYANT ANDRES ,  IEONG MEIKEI ,  MULLER K PAUL ,  NOWAK EDWARD J ,  FRIED DAVID M ,  RANKIN JED

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/28

CPC classification number: H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and -0.5V for pFETs.

Abstract translation: 因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。 通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。 特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。 例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

公开(公告)号：EP1639648A4

公开(公告)日：2007-05-30

申请号：EP04777432

申请日：2004-06-30

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L29/06 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

公开(公告)号：JP2004088089A

公开(公告)日：2004-03-18

申请号：JP2003184250

申请日：2003-06-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BROWN JEFFREY S ,  FRIED DAVID M ,  EDWARD J NOWACK ,  RAINEY BETH ANN

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/108 ,  H01L27/10873 ,  H01L28/90 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a 2-device type DRAM cell which has high soft error resistance that is one of trouble mechanisms of a DRAM, and which is simply manufactured. SOLUTION: The DRAM cell is a memory cell (two-device type DRAM) including first and second transfer devices in a completely deplete state each including one body(semiconductor rail), and first and second diffusion electrodes. The DRAM cell further includes a difference storage capacitor which has at least one node that is adjacent to the first and the second diffusion electrodes of each transfer device, and is electrically connected with the same. The difference storage capacitor includes a main capacitor and a plurality of specific capacitors, and the main capacitor has electrostatic capacitance at least 5 times larger than that of the plurality of the specific capacitors. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003264232A

公开(公告)日：2003-09-19

申请号：JP2003008671

申请日：2003-01-16

Applicant: IBM

Inventor： FRIED DAVID M ,  LEIPOLD WILLIAM C ,  EDWARD J NOWAKU

IPC: G06F17/50 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for generating a set of FinFET shapes. SOLUTION: The position of a gate in an FET layout is detected and a set of FinFET shapes matching the gate is generated. More specifically, the method for generating a set of FinFET shapes comprises a step for detecting the position of a gate in an FET layout, a step for finding the axis of the gate, a step for generating a set of FinFET shapes matching the gate, and a step for elongating the set of FinFET shapes perpendicularly to the gate axis. Furthermore, an FinFET layout can be created by correcting the FET layout to include a set of FinFET shapes. More specifically, the system for generating a set of FinFET shapes comprises a subsystem for detecting the position of a gate in an FET layout, and a subsystem for generating a set of FinFET shapes matching the gate. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003318286A

公开(公告)日：2003-11-07

申请号：JP2003107565

申请日：2003-04-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： FRIED DAVID M ,  EDWARD J NOWAKU ,  RAINEY BETH ANN

IPC: H01L21/8242 ,  H01L21/336 ,  H01L21/84 ,  H01L27/02 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L31/0328

CPC classification number: H01L27/10838 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10888 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell, and its fabricating method, in which cell density can be increased without increasing the fabrication cost or the complicacy excessively.
SOLUTION: A fin arrangement forming a memory cell is provided. More concretely, an access transistor is provided by forming a finned field effect transistor (FET) and a storage capacitor is provided by forming a finned capacitor. When the memory cell is formed using a finned FET and a finned capacitor, memory cell density can be increased significantly as compared with the conventional planar capacitor arrangement. Furthermore, a memory cell can be fabricated with significantly lower process cost and complicacy than those of the conventional deep trench capacitor arrangement.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种其中可以增加细胞密度而不增加制造成本或过度复杂的存储单元及其制造方法。 提供形成存储单元的翅片布置。 更具体地，通过形成翅片场效应晶体管（FET）提供存取晶体管，并且通过形成鳍式电容器来提供存储电容器。 当使用有鳍FET和鳍状电容器形成存储单元时，与常规平面电容器布置相比，可以显着提高存储单元密度。 此外，与传统的深沟槽电容器布置相比，可以以显着更低的工艺成本和复杂性制造存储器单元。 版权所有（C）2004，JPO

公开(公告)号：EP1488462A4

公开(公告)日：2008-04-23

申请号：EP03719421

申请日：2003-03-19

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FRIED DAVID M ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/786 ,  H01L29/78 ,  H01L33/00

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

Abstract: A structure for a transistor that includes an insulator (10) and a silicon structure on the insulator. The silicon structure includes a central portion (155) and Fins (250) extending from ends of the central portion. A first gate (50) is positioned on a first side of the central portion of the silicon structure. A strain-producing layer (11) could be between the first gate (50) and the first side of the central portion (155) of the silicon structure and a second gate (160) is on a second side of the central portion (155) of the silicon structure.

公开(公告)号：EP1581968A4

公开(公告)日：2007-04-18

申请号：EP02808339

申请日：2002-12-20

Applicant: IBM

Inventor： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M

IPC: H01L23/525 ,  H01L21/82 ,  H01L21/84 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).

公开(公告)号：EP1573804A4

公开(公告)日：2006-03-08

申请号：EP02798557

申请日：2002-12-19

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETHANN

IPC: H01L21/84 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L21/823437 ,  H01L29/42384 ,  H01L29/66795

Abstract: Methods for forming a spacer (44) for a first structure (24, 124), such as a gate structure of a FinFET, and at most a portion of a second structure (14), such as a fin, without detrimentally altering the second structure. The methods generate a first structure (24) having a top portion (30, 130) that overhangs an electrically conductive lower portion (32, 132) and a spacer (44) under the overhang (40, 140). The overhang (40, 140) may be removed after spacer processing. Relative to a FinFET, the overhang protects parts of the fin (14) such as regions adjacent and under the gate structure (24, 124) , and allows for exposing sidewalls of the fin (14) to other processing such as selective silicon growth and implantation. As a result, the methods allow sizing of the fin (14) and construction of the gate structure (24, 124) and spacer without detrimentally altering (e.g., eroding by forming a spacer thereon) the fin (14) during spacer processing. A FinFET (100) including a gate structure (24, 124) and spacer (44) is also disclosed.

公开(公告)号：WO2005004206A3

公开(公告)日：2005-02-17

申请号：PCT/US2004021279

申请日：2004-06-30

Applicant: IBM ,  BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L21/308 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/06 ,  H01L21/00 ,  H01L21/8238 ,  H01L29/76

CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

Abstract translation: 公开了一种利用互补鳍型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片（100）的第一类型FinFET以及包括平行于第一鳍片（100）延伸的第二鳍片（102）的第二类型FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域（130）与第二类型FinFET之间的绝缘体鳍状物。 绝缘体鳍状物具有与第一鳍状物（100）和第二鳍状物（102）大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个 鳍。 本发明还具有在第一类型FinFET和第二类型FinFET的沟道区上形成的共同栅极（106）。 栅极（106）包括与第一类型FinFET相邻的第一杂质掺杂区域和与第二类型FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型的FinFET和第二类型的FinFET之间的差异有关的不同的功函数。 第一翅片（100）和第二翅片（102）具有大致相同的宽度。