公开(公告)号：EP2130276A4

公开(公告)日：2012-01-18

申请号：EP08744599

申请日：2008-03-28

Applicant: IBM

Inventor： ABOU-KHALIL MICHEL J ,  GAUTHIER ROBERT ,  LI HONGMEI ,  LI JUNJUN ,  MITRA SOUVICK ,  PUTNAM CHRISTOPHER S

IPC: H02H9/00 ,  H01L27/02

CPC classification number: H01L27/0277 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1639648A4

公开(公告)日：2007-05-30

申请号：EP04777432

申请日：2004-06-30

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L29/06 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

公开(公告)号：WO2011002612A3

公开(公告)日：2011-03-10

申请号：PCT/US2010038934

申请日：2010-06-17

Applicant: IBM ,  ABOU-KHALIL MICHEL J ,  LEE TOM C ,  LI JUNJUN ,  GAUTHIER ROBERT J JR ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK

Inventor： ABOU-KHALIL MICHEL J ,  LEE TOM C ,  LI JUNJUN ,  GAUTHIER ROBERT J JR ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK

IPC: H01L21/82 ,  H01L27/02

CPC classification number: G11C17/16 ,  G11C11/5692 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse (150) has two short high atomic diffusion resistance conductor layers (110, 130) positioned on opposite sides (121, 122) and at a same end (123) of a long low atomic diffusion resistance conductor layer (120). A voltage source (170) is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals (first terminal = 170/161/110; second terminal = 170/162/130; third terminal = 170/163/proximate end 123 of conductor layer 120; and, fourth terminal = 170/164/distal end 124 of conductor layer 120) in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces (125, 126). The formation of such opens and/or shorts can be used to achieve different programming states (11, 01, 10, 00). Other circuit structure embodiments incorporate e-fuses (650) with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

Abstract translation: 公开了电子熔丝编程/重新编程电路的实施例。 在一个实施例中，电子熔丝（150）具有两个短的高原子扩散电阻导体层（110,130），其位于长的低原子扩散电阻导体（110,130）的相对侧（121,122）上和同一端（123） 层（120）。 使用电压源（170）来改变施加到端子（第一端= 170/161/110;第二端= 170/162/130;第三端= 170/163 / 以控制导体层120的近端123;以及导体层120的第四端子= 170/164 /远端124），以便控制长导体层内电子的双向流动，从而形成开路和/或短路 在长导体层 - 短导体层界面（125,126）处。 这种开路和/或短路的形成可以用来实现不同的编程状态（11,01,10,00）。 其他电路结构实施例将e熔丝（650）与额外的导体层和额外的端子结合，以允许更多的编程状态。 还公开了相关联的电子熔丝编程和重新编程方法的实施例。

公开(公告)号：WO2012177380A3

公开(公告)日：2013-02-28

申请号：PCT/US2012040849

申请日：2012-06-05

Applicant: IBM ,  THOMPSON ERIC ,  BOOTH JR ROGER A ,  LU NING ,  PUTNAM CHRISTOPHER S

Inventor： THOMPSON ERIC ,  BOOTH JR ROGER A ,  LU NING ,  PUTNAM CHRISTOPHER S

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L23/5223 ,  H01L27/0207 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal capacitor structure includes a plurality of line level structures (15, 16, 25, 26) vertically interconnected with via level structures (31, 32, 33, 34, 41, 42). Each first line level structure (15 or 25) and each second line level structure (16 or 26) includes a set of parallel metal lines (11 or 21, 12 or 22) that is physically joined at an end to a rectangular tab structure (13 or 23, 14 or 24) having a rectangular horizontal cross-sectional area. A first set of parallel metal lines (11 or 21) within a first line level structure (15 or 25) and a second set of parallel metal lines (12 or 22) within a second line level structure (16 or 26) are interdigitated and parallel to each other, and can collectively form an interdigitated uniform pitch structure ((11, 12) or (21, 22)). Because the rectangular tab structures (13 or 23, 14 or 24) do not protrude toward each other within a region between two facing sidewalls of the rectangular tab structures (13 or 23, 14 or 24), sub- resolution assist features (SRAFs) can be employed to provide a uniform width and a uniform pitch throughout the entirety of the interdigitated uniform pitch structure ((11, 12) or (21, 22)).

Abstract translation: 金属电容器结构包括与通孔级结构（31,32,33,34,41,42）垂直互连的多个线路层结构（15,16,25,26）。 每个第一线路层结构（15或25）和每个第二线路层结构（16或26）包括一组平行金属线（11或21,12或22），其在端部处物理地连接到矩形突起结构（ 13或23,14或24）具有矩形水平横截面积。 在第二行级结构（16或26）内的第一行级结构（15或25）和第二组平行金属线（12或22）内的第一组平行金属线（11或21）被交叉指向， 彼此平行，并且可以共同形成叉指均匀间距结构（（11,12）或（21,22））。 因为矩形突片结构（13或23,14或24）在矩形突片结构（13或23,14或24）的两个相对的侧壁之间的区域内不会彼此突出，所以分解辅助特征（SRAF） 可以用于在整个交叉的均匀间距结构（（11,12）或（21,22））的整个上提供均匀的宽度和均匀的间距。

公开(公告)号：WO2005004206A3

公开(公告)日：2005-02-17

申请号：PCT/US2004021279

申请日：2004-06-30

Applicant: IBM ,  BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L21/308 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/06 ,  H01L21/00 ,  H01L21/8238 ,  H01L29/76

CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

Abstract translation: 公开了一种利用互补鳍型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片（100）的第一类型FinFET以及包括平行于第一鳍片（100）延伸的第二鳍片（102）的第二类型FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域（130）与第二类型FinFET之间的绝缘体鳍状物。 绝缘体鳍状物具有与第一鳍状物（100）和第二鳍状物（102）大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个 鳍。 本发明还具有在第一类型FinFET和第二类型FinFET的沟道区上形成的共同栅极（106）。 栅极（106）包括与第一类型FinFET相邻的第一杂质掺杂区域和与第二类型FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型的FinFET和第二类型的FinFET之间的差异有关的不同的功函数。 第一翅片（100）和第二翅片（102）具有大致相同的宽度。

公开(公告)号：DE602004015793D1

公开(公告)日：2008-09-25

申请号：DE602004015793

申请日：2004-06-30

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L29/06 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786

公开(公告)号：GB2483612A

公开(公告)日：2012-03-14

申请号：GB201200546

申请日：2010-06-17

Applicant: IBM

Inventor： ABOU-KHALIL MICHEL J ,  LEE TOM C ,  GAUTHIER JR ROBERT J ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK ,  LI JUNJUN

IPC: H01L21/82 ,  H01L27/02

Abstract: Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse (150) has two short high atomic diffusion resistance conductor layers (110, 130) positioned on opposite sides (121, 122) and at a same end (123) of a long low atomic diffusion resistance conductor layer (120). A voltage source (170) is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals (first terminal = 170/161/110; second terminal = 170/162/130; third terminal = 170/163/proximate end 123 of conductor layer 120; and, fourth terminal = 170/164/distal end 124 of conductor layer 120) in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces (125, 126). The formation of such opens and/or shorts can be used to achieve different programming states (11, 01, 10, 00). Other circuit structure embodiments incorporate e-fuses (650) with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

公开(公告)号：GB2505613A

公开(公告)日：2014-03-05

申请号：GB201322254

申请日：2012-06-05

Applicant: IBM

Inventor： THOMPSON ERIC ,  BOOTH JR ROGER ,  LU NING ,  PUTNAM CHRISTOPHER S

IPC: H01L23/528 ,  H01G4/012

Abstract: A metal capacitor structure includes a plurality of line level structures (15, 16, 25, 26) vertically interconnected with via level structures (31, 32, 33, 34, 41, 42). Each first line level structure (15 or 25) and each second line level structure (16 or 26) includes a set of parallel metal lines (11 or 21, 12 or 22) that is physically joined at an end to a rectangular tab structure (13 or 23, 14 or 24) having a rectangular horizontal cross-sectional area. A first set of parallel metal lines (11 or 21) within a first line level structure (15 or 25) and a second set of parallel metal lines (12 or 22) within a second line level structure (16 or 26) are interdigitated and parallel to each other, and can collectively form an interdigitated uniform pitch structure ((11, 12) or (21, 22)). Because the rectangular tab structures (13 or 23, 14 or 24) do not protrude toward each other within a region between two facing sidewalls of the rectangular tab structures (13 or 23, 14 or 24), sub- resolution assist features (SRAFs) can be employed to provide a uniform width and a uniform pitch throughout the entirety of the interdigitated uniform pitch structure ((11, 12) or (21, 22)).

公开(公告)号：GB2483612B

公开(公告)日：2013-07-10

申请号：GB201200546

申请日：2010-06-17

Applicant: IBM

Inventor： ABOU-KHALIL MICHEL J ,  LEE TOM C ,  GAUTHIER JR ROBERT J ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK ,  LI JUNJUN

IPC: H01L21/82 ,  H01L27/02

Abstract: In one embodiment of an e-fuse programming/re-programming circuit, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

公开(公告)号：GB2497704A

公开(公告)日：2013-06-19

申请号：GB201306287

申请日：2011-09-14

Applicant: IBM

Inventor： ABOU-KHALIL MICHEL J ,  GAUTHIER JR ROBERT J ,  LEE TOM C ,  LI JUNJUN ,  MITRA SOUVICK ,  PUTNAM CHRISTOPHER S

IPC: H01L27/02

Abstract: Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode (10a) of a first of the back-to-back stacked SCR (10) is connected to an input (30). An anode (20a) of a second of the back-to-back stacked SCR (20) is connected to ground (GND). Cathodes (10b, 20b) of the first and second of the back- to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes (Di, D2) directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes (D3, D4) of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.