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    MICRO-ELECTROMECHANICAL SWITCH HAVING A DEFORMABLE ELASTOMERIC CONDUCTIVE ELEMENT
    2.
    发明公开
    MICRO-ELECTROMECHANICAL SWITCH HAVING A DEFORMABLE ELASTOMERIC CONDUCTIVE ELEMENT 审中-公开
    微机电开关，可变形的弹性LEITFüHIGEN元

    公开(公告)号：EP1535296A4

    公开(公告)日：2007-04-04

    申请号：EP02746591

    申请日：2002-06-14

    Applicant: IBM

    Inventor： DELIGIANNI HARIKLIA ,  GREENBERG DAVID R ,  JAHNES CHRISTOPHER V ,  LUND JENNIFER L ,  SAENGER KATHERINE L ,  VOLANT RICHARD P

    IPC: H01H57/00 ,  H01H59/00 ,  H01L21/00

    CPC classification number: H01H59/0009

    Abstract: A micro-electromechanical switch (MEMS) having a deformable elastomeric element (1) which exhibits a large change in conductivity with a small amount of displacement. The deformable elastomeric element (1) is displaced by an electrostatic force that is applied laterally resulting in a small transverse displacement. The transversal displacement, in turn, pushes a metallic contact (7) against two conductive paths (5, 6), allowing passage of electrical signals. The elastomer (1) is provided on two opposing sids with embedded metallic elements (9, 10), such as impregnated metallic rods, metallic sheets, metallic particles, or conductive paste. Actuation electrodes (18, 8) are placed parallel to the conductive sides of the elastomer. A voltage applied between the conductive side of the elastomer and the respective actuation electrodes (18, 8) generate the electrostatic attractive force that compresses the elastomer (1), creating the transverse displacement that closes the MEMS. The elastomeric based MEMS extends the lifetime of the switch by extending fatigue life of the deformable switch elements.

    HETERO-JUNCTION BIPOLAR TRANSISTOR AND ITS MANUFACTURING METHOD
    3.
    发明专利
    HETERO-JUNCTION BIPOLAR TRANSISTOR AND ITS MANUFACTURING METHOD 审中-公开

    公开(公告)号：JP2002329725A

    公开(公告)日：2002-11-15

    申请号：JP2002104250

    申请日：2002-04-05

    Applicant: IBM

    Inventor： GREGORY G FREEMAN ,  GREENBERG DAVID R ,  JENG SHWU-JEN

    IPC: H01L21/331 ,  H01L29/10 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To provide a method to form a high performance hetero-junction bipolar transistor. SOLUTION: The invention includes a process to form two pairs of spacers at both ends of an emitter pedestal. After a first pair of spacers 130 is formed, a first outer base region 100 is formed at both ends of an intrinsic base. A second pair of spacers 160 is formed above the first pair of spacers 130. Then, a second outer base region 140 is formed at both ends of the intrinsic base. Two pairs of spacers enable the first outer base and the second outer base to have different widths. This brings about a structure of complex outer base that is adjacent to an emitter 22 and not adjacent to a collector 20 and consequently a base parasitic resistance reduces with the reduction of parasitic capacitance between the collector and outer base.

    MULTI-LEVEL INTERCONNECTIONS FOR AN INTEGRATED CIRCUIT CHIP
    4.
    发明申请
    MULTI-LEVEL INTERCONNECTIONS FOR AN INTEGRATED CIRCUIT CHIP 审中-公开
    集成电路芯片的多级互连

    公开(公告)号：WO2007002158A2

    公开(公告)日：2007-01-04

    申请号：PCT/US2006024085

    申请日：2006-06-21

    Applicant: IBM ,  GREENBERG DAVID R ,  PEKARIK JOHN J ,  SCHOLVIN JORG

    Inventor： GREENBERG DAVID R ,  PEKARIK JOHN J ,  SCHOLVIN JORG

    IPC: H01L23/52

    CPC classification number: H01L23/528 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Multilevel metallization layouts for an integrated circuit chip (30) including transistors having first (31 ), second (32) and third (33) elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection (39) for the second contact vertically (32) from the chip (30), overlapping the planes and fingers of the metallization layouts to the first and second elements (31 ) and (32) and forming a pyramid or staircase of multilevel metallization layers (45) and (46) to smooth diagonal current flow.

    Abstract translation: 用于集成电路芯片（30）的多层金属化布局包括具有金属化布局连接的第一（31），第二（32）和第三（33）元件的晶体管。 布局通过将来自芯片（30）的垂直（32）的第二触点的连接（39）定位成与金属化布局的平面和手指重叠到第一和第二元件（31）和（ 32）并且形成多层金属化层（45）和（46）的金字塔或楼梯以平滑对角线电流。

    Transistor structure having minimized parasitic effect and manufacturing method of same
    5.
    发明专利
    Transistor structure having minimized parasitic effect and manufacturing method of same 有权
    具有最小化的PARASITIC效应的晶体管结构及其制造方法

    公开(公告)号：JP2005244225A

    公开(公告)日：2005-09-08

    申请号：JP2005045016

    申请日：2005-02-22

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： GREENBERG DAVID R ,  JENG SHWU-JEN

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/423 ,  H01L29/72 ,  H01L29/73 ,  H01L29/732

    CPC classification number: H01L29/66287 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42308 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

    Abstract: PROBLEM TO BE SOLVED: To provide a transistor having a minimized parasitic effect. SOLUTION: The transistor includes an emitter, having a recessed extrinsic emitter portion on an intrinsic emitter portion, and an intrinsic base portion electrically contacted with the intrinsic emitter portion and an extrinsic base portion electrically contacted with the intrinsic base portion, and also includes a base electrically isolated from a recessed extrinsic emitter portion by means of a pair of emitter/base spacers and a collector electrically contacted with the intrinsic base portion. The transistor can further include an intrinsic base, having a completely silicide upper surface, until it reaches the emitter/base spacers. The transistor can further include a base window opening in an active region. A method of forming the transistor is also included. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供具有最小化的寄生效应的晶体管。 解决方案：晶体管包括发射极，在本征发射极部分具有凹入的非本征发射极部分，以及与本征发射极部分电接触的本征基极部分和与本征基极部分电接触的非本征基极部分，以及 包括通过一对发射极/基极间隔物和与本征基极部电接触的集电体与凹入的外部发射极部分电隔离的基极。 晶体管可以进一步包括具有完全硅化物上表面的本征基极，直至其到达发射极/基极间隔物。 晶体管还可以包括在有源区域中的基部窗口开口。 还包括形成晶体管的方法。 版权所有（C）2005，JPO＆NCIPI

    FINE ELECTRIC MECHANICAL SWITCH
    6.
    发明专利
    FINE ELECTRIC MECHANICAL SWITCH 审中-公开

    公开(公告)号：JP2003249137A

    公开(公告)日：2003-09-05

    申请号：JP2002330991

    申请日：2002-11-14

    Applicant: IBM

    Inventor： GREENBERG DAVID R ,  DELIGIANNI HARIKLIA ,  ROBERT A GROVES ,  CHRISTOPHER V JARNES ,  LUND JENNIFER L ,  CATHERINE L SAENGER ,  VOLANT RICHARD P

    IPC: B81B3/00 ,  H01H1/24 ,  H01H1/26 ,  H01H59/00

    Abstract: PROBLEM TO BE SOLVED: To provide a fine electric mechanical switch having a restoring force large enough to overcome static friction. SOLUTION: This fine electric mechanical switch comprises a conductive beam 10 capable of being warped, and a plurality of electrodes which are covered with elastically deformable conductive layers 11. At first, a restoring force is generated by a single spring constant k0 of the beam 10 by applying a control voltage between the beam 10 capable of being warped and a control electrode 12 which is flush with a switch electrode 13. Then, when the fine electric mechanical switch is approached to the closed state and the conductive layers 11 are compressed, restoring forces due to additional spring constants, k1,..., kn of the plurality of deformable conductive layers 11 are sequentially added to the restoring force due to the spring constant k0 of the beam 10. In another embodiment, deformable spring-like elements are used in place of the deformable layers. Furthermore in the other embodiment, compressible layers or the deformable spring-like elements are mounted on the warping beam which is opposed to the switch electrode. COPYRIGHT: (C)2003,JPO

    7.
    发明专利
    未知

    公开(公告)号：DE60128883D1

    公开(公告)日：2007-07-26

    申请号：DE60128883

    申请日：2001-12-10

    Applicant: IBM

    Inventor： GREENBERG DAVID R ,  JADUS DALE K ,  SUBBANNA SESHARDRI ,  WALTER KEITH M

    IPC: H01L29/868 ,  H01L21/329

    Abstract: The invention provides a PIN diode having a laterally extended I-region (5). The invention also provides a method of fabricating the inventive PIN diode compatible with modern RF technologies such as silicon-germanium BiCMOS processes.

    8.
    发明专利
    未知

    公开(公告)号：AT364901T

    公开(公告)日：2007-07-15

    申请号：AT01310302

    申请日：2001-12-10

    Applicant: IBM

    Inventor： GREENBERG DAVID R ,  JADUS DALE K ,  SUBBANNA SESHARDRI ,  WALTER KEITH M

    IPC: H01L29/868 ,  H01L21/329

    Abstract: The invention provides a PIN diode having a laterally extended I-region (5). The invention also provides a method of fabricating the inventive PIN diode compatible with modern RF technologies such as silicon-germanium BiCMOS processes.

    9.
    发明专利
    未知

    公开(公告)号：DE60128883T2

    公开(公告)日：2008-02-14

    申请号：DE60128883

    申请日：2001-12-10

    Applicant: IBM

    Inventor： GREENBERG DAVID R ,  JADUS DALE K ,  SUBBANNA SESHARDRI ,  WALTER KEITH M

    IPC: H01L29/868 ,  H01L21/329

    Abstract: The invention provides a PIN diode having a laterally extended I-region (5). The invention also provides a method of fabricating the inventive PIN diode compatible with modern RF technologies such as silicon-germanium BiCMOS processes.

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