公开(公告)号：EP1371091A4

公开(公告)日：2009-04-01

申请号：EP01990800

申请日：2001-12-04

Applicant: IBM

Inventor： GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76835 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. The control over the conductor resistance is obtained using a buried etch stop layer (56) having a second atomic composition located between the line and via dielectric layers (54', 58') of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask (60) which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

公开(公告)号：EP1371090A4

公开(公告)日：2007-10-24

申请号：EP01990106

申请日：2001-12-10

Applicant: IBM

Inventor： GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763 ,  H01L23/48

CPC classification number: H01L21/76835 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/76811

Abstract: A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics. Moreover, the spun-on dielectrics of the hybrid low-k dielectric have distinctly different atomic compositions enabling control over the conductor resistance using the bottom spun-on dielectric (i.e., via dielectric) as an inherent etch stop layer for the upper spun-on dielectric (i.e., line dielectric).

公开(公告)号：JP2002270612A

公开(公告)日：2002-09-20

申请号：JP2002037664

申请日：2002-02-15

Applicant: IBM

Inventor： FORNOF ANN RHEA-HELENE ,  GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CHRISTY SENSENICH

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a simple method where cost effect for patterning a mutual connection structure, in which the material subjected to spin-on is used as a hard mask, is high. SOLUTION: By using the material subjected to spin-on processing to the hard mask, a process can be executed by using a single tool, and usage of a single curing step is enhance, which is not normally used in a patterning process of the conventional technique, in which a CVD hard mask is used. Selection of a polishing stop layer (formed on a surface of low k dielectrics), which has permittivity nearly equal to that of dielectrics positioned below is enabled by using spin coating, so that effective permittivity of an obtained structure is not significantly increased. The hard mask used contains, at least two kinds of spin-on dielectric materials having different etching speeds.

公开(公告)号：JP2002319621A

公开(公告)日：2002-10-31

申请号：JP2002035811

申请日：2002-02-13

Applicant: IBM

Inventor： GATES STEPHEN MCCONNELL ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  TYBERG CRISTY SENSENICH

IPC: H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide an interconnecting structure containing patterned multilayered spun-on dielectrics, and to provide a method of forming the structure. SOLUTION: The interconnecting structure contains the patterned multilayered spun-on dielectrics 12' formed on the surface of a substrate. The dielectrics 12 are constituted of a lower low-k dielectrics 14', an embedded etch stop layer 16', and an upper low-k dielectric 18'. The dielectrics 14' and 18' have a first composition and the layer 16' has a second composition which is different from the first composition and is covalently coupled with the dielectrics 14' and 18'. The mutual connecting structure also contains a polish stop layer 22' formed on the multilayered spun-on dielectrics 12' and a metal conductive region 34 formed in the dielectrics 12'.

公开(公告)号：WO02069381A2

公开(公告)日：2002-09-06

申请号：PCT/US0204879

申请日：2002-02-19

Applicant: IBM

Inventor： ECKERT ANDREW ROBERT ,  HAY JOHN C ,  HEDRICK JEFFREY CURTIS ,  LEE KANG-WOOK ,  LINIGER ERIC GERHARD ,  SIMONYI EVA ERIKA

IPC: H01L21/312 ,  H01L21/768

CPC classification number: H01L21/02282 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3124 ,  H01L21/76829

Abstract: A substantially defect-free, low-k dielectric film having improved adhesion is provided by (a) applying a silane coupling agent containing at least one polymerizable group to a surface of a substrate so as to provide a substantially uniform coating of said silane-coupling agent on said substrate; (b) heating the substrate containing the coating of the silane-coupling agent at a temperature of about 90°C or above so as to provide a surface containing Si-O bonds; (c) rinsing the heated substrate with a suitable solvent that is effective in removing any residual silane-coupling agent; and (d) applying a dielectric material to the rinsed surface containing the Si-O bonds.

Abstract translation: 通过（a）将含有至少一个可聚合基团的硅烷偶联剂施加到基材的表面来提供具有改善的粘合性的基本上无缺陷的低k电介质膜，以便提供所述硅烷偶联剂的基本上均匀的涂层 剂; （b）在约90℃以上的温度下加热含有硅烷偶联剂涂层的基材，以提供含有Si-O键的表面; （c）用有效去除任何残留的硅烷偶联剂的合适溶剂漂洗加热的基底; 和（d）将介电材料施加到含有Si-O键的漂洗表面上。

公开(公告)号：JP2005175479A

公开(公告)日：2005-06-30

申请号：JP2004353505

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN SHYNG-TSONG ,  CHIRAS STEFANIE R ,  COLBURN MATTHEW EARL ,  DALTON TIMOTHY JOSEPH ,  HEDRICK JEFFREY CURTIS ,  HUANG ELBERT EMIN ,  KUMAR KAUSHIK A ,  LANE MICHAEL WAYNE ,  MALONE KELLY ,  NARAYAN CHANDRASEKHAR ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  ROSENBERG ROBERT ,  TYBERG CHRISTY S ,  YU ROY RONGQING

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure which reduces the dielectric constant between conductive lines by providing an air dielectric. SOLUTION: In a multilevel microelectronic integrated circuit, air comprises a permanent line level dielectric, and an ultra-low-k material constitutes a via level dielectric. In the IC structure, air is supplied to the line level after removal of a sacrificial material by clean thermal decomposition and auxiliary diffusion of byproducts through porosities. Optionally, air is also included within porosities in the via level dielectric. By incorporating air into the extension produced in the invention, intralevel and interlevel dielectric values are minimized. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过提供空气电介质来降低导线之间的介电常数的结构。 解决方案：在多电平微电子集成电路中，空气包括永久线路电平介质，超低k材料构成通孔级电介质。 在IC结构中，通过清洁的热分解和副产物通过孔隙的辅助扩散除去牺牲材料之后，空气被提供给线路层。 任选地，空气也包括在通孔级电介质中的孔隙中。 通过将空气并入本发明中生产的延伸中，使层内和层间介电值最小化。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2001085419A

公开(公告)日：2001-03-30

申请号：JP2000236834

申请日：2000-08-04

Applicant: IBM

Inventor： STEPHAN ALAN COEN ,  CLADIUS FEEGAA ,  HEDRICK JEFFREY CURTIS ,  SHAW JANE MARGARET

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/312 ,  H01L21/314 ,  H01L23/532 ,  H01L29/51

Abstract: PROBLEM TO BE SOLVED: To reduce Cu ion migration by allowing an interlayer dielectrics to comprise a dielectric material whose permittivity is a specified value or below as well as additives, and combining the additives to the Cu ion. SOLUTION: An interlayer dielectrics 12 is formed on a substrate 10, comprising such semiconductor material as Si, Ge, GaAs, InAs, InP, or other III/V compound. The interlayer dielectrics 12 comprises such amount of additives as effective for combination with Cu ion, as well as a dielectrics of low permittivity which comprises polyimide, polyamide, diamond, diamond-like carbon, silicon-contained polymer, polyallylene ether, paralien polymer, and organic dielectric material of permittivity 3.0 or below. Thus, Cu ion migration is reduced.

公开(公告)号：IN1322DE2003A

公开(公告)日：2005-05-27

申请号：IN1322DE2003

申请日：2003-08-19

Applicant: IBM

Inventor： ECKERT ANDREW ROBERT ,  HAY JOHN C ,  HEDRICK JEFFREY CURTIS ,  LEE KANG-WOOK ,  LINIGER ERIC GERHARD ,  SIMONYI EVA ERIKA

IPC: H01L21/312 ,  H01L21/768

Abstract: A substantially defect-free, low-k dielectric film having improved adhesion is provided by (a) applying a silane coupling agent containing at least one polymerizable group to a surface of a substrate so as to provide a substantially uniform coating of said silane-coupling agent on said substrate; (b) heating the substrate containing the coating of the silane-coupling agent at a temperature of about 90° C. or above so as to provide a surface containing Si-O bonds; (c) rinsing the heated substrate with a suitable solvent that is effective in removing any residual silane-coupling agent; and (d) applying a dielectric material to the rinsed surface containing the Si-O bonds.

公开(公告)号：HK1055641A1

公开(公告)日：2004-01-16

申请号：HK03107854

申请日：2003-10-31

Applicant: IBM

Inventor： DALTON TIMOTHY JOSEPH ,  GRECO STEPHEN EDWARD ,  HEDRICK JEFFREY CURTIS ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  RODBELL KENNETH PARKER ,  ROSENBERG ROBERT

IPC: H01L21/316 ,  H01L21/31 ,  H01L21/768 ,  H01L23/532 ,  H01L

Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus forming a dielectric material that has a low dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.

公开(公告)号：ES2262797T3

公开(公告)日：2006-12-01

申请号：ES02721047

申请日：2002-02-19

Applicant: IBM

Inventor： ECKERT ANDREW ROBERT ,  HAY JOHN C ,  HEDRICK JEFFREY CURTIS ,  LEE KANG-WOOK ,  LINIGER ERIC GERHARD ,  SIMONYI EVA ERIKA

IPC: H01L21/312 ,  H01L21/768

Abstract: Un método de fabricación de un circuito integrado que comprende las etapas de: (a) aplicar un agente de copulación de silano que con- tiene al menos un grupo polimerizable a una superficie de un substrato (10) de tal manera como para proporcionar un revestimiento sustancialmente uniforme (12) de dicho agente de copulación de silano sobre dicho substrato; (b) calentar dicho substrato que contiene dicho reves- timiento de dicho agente de copulación de silano a una tem- peratura de 90ºC o superior para proporcionar una capa superficial modificada (14) a dicho substrato que contiene enlaces Si-O; (c) enjuagar dicho substrato calentado con un disol- vente adecuado que es eficaz para separar cualquier agente de copulación de silano sin reaccionar; y (d) aplicar un material dieléctrico (16) a dicha su- perficie enjuagada que contiene dichos enlaces Si-O.