公开(公告)号：EP1366512A4

公开(公告)日：2009-07-08

申请号：EP01987440

申请日：2001-12-19

Applicant: IBM

Inventor： WALKER GEORGE F ,  GOLDBLATT RONALD D ,  GRUBER PETER A ,  HORTON RAYMOND R ,  PETRARCA KEVIN S ,  VOLANT RICHARD P ,  CHENG TIEN-JEN

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485 ,  H01L21/44 ,  H01L23/48

CPC classification number: H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract translation: 描述了用于形成适用于引线键合和焊料凸点倒装芯片连接（例如可控塌陷芯片连接（C4））的公共输入 - 输出（I / O）位置的过程。 本发明特别适用于使用铜作为互连材料的半导体芯片，其中用于制造这种芯片的软电介质容易因结合力而损坏。 本发明通过在衬垫的顶表面上提供具有贵金属的部位，同时提供扩散阻挡层以维持金属互连的高导电性，从而降低了损坏的风险。 通过提供在衬底中形成的特征中选择性地沉积金属层的方法来减少用于在衬底内形成I / O部位的工艺步骤。 由于本发明的I / O站点可以用于引线键合或焊料凸点连接，这为芯片互连选项提供了增加的灵活性，同时还降低了工艺成本。

公开(公告)号：EP1883961A4

公开(公告)日：2012-12-05

申请号：EP06759690

申请日：2006-05-12

Applicant: IBM

Inventor： CASEY JON A ,  BERGER MICHAEL ,  BUCHWALTER LEENA P ,  CANAPERI DONALD F ,  HORTON RAYMOND R ,  JAIN ANURAG ,  PERFECTO ERIC D ,  TORNELLO JAMES A

IPC: H01L23/14 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2005142562A

公开(公告)日：2005-06-02

申请号：JP2004319023

申请日：2004-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： PAUL S ANDREE ,  CASEY JON A ,  HORTON RAYMOND R ,  PATEL CHIRAQ S ,  SPROGIS EDMUND J ,  SUNDLOF BRIAN R

IPC: H01L23/12 ,  H01L21/48 ,  H01L21/60 ,  H01L21/76 ,  H01L23/14 ,  H01L25/04 ,  H01L25/18 ,  H05K3/34

CPC classification number: H01L21/486 ,  H01L23/147 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for filling a via within a wafer, particularly, for filling a blind via first, and various devices for carrying out the method. SOLUTION: The method includes a step for evacuating the via of air, a step for trapping at least a portion of a wafer and a paste with which to fill the via between two surfaces, and a step for filling the via by applying pressure to the paste. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于在晶片内填充通孔的方法，特别是用于首先填充盲孔，以及用于执行该方法的各种装置。 解决方案：该方法包括用于抽空空气通道的步骤，用于捕获至少一部分晶片和用于填充两个表面之间的通孔的浆料的步骤，以及通过施加填充通孔的步骤 对浆糊的压力。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2006124607A3

公开(公告)日：2007-04-12

申请号：PCT/US2006018458

申请日：2006-05-12

Applicant: IBM ,  CASEY JON A ,  BERGER MICHAEL ,  BUCHWALTER LEENA P ,  CANAPERI DONALD F ,  HORTON RAYMOND R ,  JAIN ANURAG ,  PERFECTO ERIC D ,  TORNELLO JAMES A

Inventor： CASEY JON A ,  BERGER MICHAEL ,  BUCHWALTER LEENA P ,  CANAPERI DONALD F ,  HORTON RAYMOND R ,  JAIN ANURAG ,  PERFECTO ERIC D ,  TORNELLO JAMES A

IPC: H01L23/22 ,  H01L23/04 ,  H01L23/14 ,  H01L23/24

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via (100) at an elevated temperature, A supply chamber (630) is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

Abstract translation: 使用无粘性，低粘度，高温稳定的聚合物或低粘度的高固含量聚合物溶液密封通孔，其中聚合物材料在高温下浸渍在通孔（100）内，引入供应室（630） 以在升高的温度下施用聚合物材料，通常在高至足以液化聚合物材料的温度下。 聚合物材料通过来自泵，活塞或保持在所述供应室内的真空的力的加热供应管线引入。

公开(公告)号：DE68905001T2

公开(公告)日：1993-09-16

申请号：DE68905001

申请日：1989-06-10

Applicant: IBM

Inventor： BICKFORD HARRY R ,  HORTON RAYMOND R ,  NOYAN ISMAIL C ,  PALMER MICHAEL J ,  ZYZO JOHN C

IPC: B23K1/012 ,  H01L21/00 ,  H01L21/60 ,  H05K3/34 ,  B23K1/00

Abstract: Method and apparatus for fluxlessly solder bonding a solder mound (2) to a solder wettable surface (8,10). A heated gas (12), preferably a reducing or non-reactive gas, is directed at a solid solder mound (2). Gas is heated to a temperature sufficient to melt solder mound. The heated gas is directed at the molten solder mound (2) at a momentum sufficient to disperse an oxide layer at the surface of the molten solder mound (2). Dispersing the oxide layer permits the molten solder to wet the solder wettable surface. The molten solder is cooled to form a solder bond.

公开(公告)号：DE68905001D1

公开(公告)日：1993-04-01

申请号：DE68905001

申请日：1989-06-10

Applicant: IBM

Inventor： BICKFORD HARRY R ,  HORTON RAYMOND R ,  NOYAN ISMAIL C ,  PALMER MICHAEL J ,  ZYZO JOHN C

IPC: B23K1/012 ,  H01L21/00 ,  H01L21/60 ,  H05K3/34 ,  B23K1/00

Abstract: Method and apparatus for fluxlessly solder bonding a solder mound (2) to a solder wettable surface (8,10). A heated gas (12), preferably a reducing or non-reactive gas, is directed at a solid solder mound (2). Gas is heated to a temperature sufficient to melt solder mound. The heated gas is directed at the molten solder mound (2) at a momentum sufficient to disperse an oxide layer at the surface of the molten solder mound (2). Dispersing the oxide layer permits the molten solder to wet the solder wettable surface. The molten solder is cooled to form a solder bond.