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    VERTICAL CURRENT CONTROLLED SILICON ON INSULATOR (SOI) DEVICE AND METHOD OF FORMING SAME
    2.
    发明申请
    VERTICAL CURRENT CONTROLLED SILICON ON INSULATOR (SOI) DEVICE AND METHOD OF FORMING SAME 审中-公开
    绝缘体上的垂直电流控制硅（SOI）器件及其形成方法

    公开(公告)号：WO2008152026A4

    公开(公告)日：2009-04-09

    申请号：PCT/EP2008057196

    申请日：2008-06-10

    Applicant: IBM ,  IBM UK ,  GAUTHIER JR ROBERT ,  LI JUNJUN ,  MITRA SOUVICK ,  PUTNAM CHRISTOPHER STEPHEN ,  MOUSA MAHMOUD

    Inventor： GAUTHIER JR ROBERT ,  LI JUNJUN ,  MITRA SOUVICK ,  PUTNAM CHRISTOPHER STEPHEN ,  MOUSA MAHMOUD

    IPC: H01L27/02 ,  H01L21/762 ,  H01L29/74

    CPC classification number: H01L27/0262

    Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

    Abstract translation: 具有诸如垂直硅控整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器之类的器件的绝缘体上硅（SOI）集成电路（IC）芯片以及制造该器件的方法 S）。 这些器件通过SOI表面层和绝缘体层形成在种子孔中以形成衬底。 通过衬底中的种子孔形成埋入式扩散，例如N型。 掺杂的外延层形成在掩埋扩散区上，并且可以包括多个掺杂层，例如P型层和N型层。 可以在掺杂的外延层上形成例如P型的多晶硅。 到埋置扩散的接触形成在接触衬垫中。

    VERTICAL CURRENT CONTROLLED SILICON ON INSULATOR (SOI) DEVICE AND METHOD OF FORMING SAME
    5.
    发明申请
    VERTICAL CURRENT CONTROLLED SILICON ON INSULATOR (SOI) DEVICE AND METHOD OF FORMING SAME 审中-公开
    绝缘体上的垂直电流控制硅（SOI）器件及其形成方法

    公开(公告)号：WO2008152026A3

    公开(公告)日：2009-02-19

    申请号：PCT/EP2008057196

    申请日：2008-06-10

    Applicant: IBM ,  IBM UK ,  GAUTHIER JR ROBERT ,  LI JUNJUN ,  MITRA SOUVICK ,  PUTNAM CHRISTOPHER STEPHEN ,  MOUSA MAHMOUD

    Inventor： GAUTHIER JR ROBERT ,  LI JUNJUN ,  MITRA SOUVICK ,  PUTNAM CHRISTOPHER STEPHEN ,  MOUSA MAHMOUD

    IPC: H01L27/02 ,  H01L21/762 ,  H01L29/74

    CPC classification number: H01L27/0262

    Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

    Abstract translation: 具有诸如垂直硅控制整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器等器件的绝缘体硅（SOI）集成电路（IC）芯片和制造器件的方法（ S）。 器件通过SOI表面层和绝缘体层形成在晶种孔中。 通过衬底中的种子孔形成例如N型的掩埋扩散。 掺杂的外延层形成在掩埋扩散层上，并且可以包括多个掺杂层，例如P型层和N型层。 可以在掺杂的外延层上形成多晶硅，例如P型。 与埋入扩散部的接触形成在接触衬里中。

    CIRCUIT STRUCTURE AND METHOD FOR PROGRAMMING AND RE-PROGRAMMING A LOW POWER, MULTIPLE STATES, ELECTRONIC FUSE(E-FUSE)
    6.
    发明申请
    CIRCUIT STRUCTURE AND METHOD FOR PROGRAMMING AND RE-PROGRAMMING A LOW POWER, MULTIPLE STATES, ELECTRONIC FUSE(E-FUSE) 审中-公开
    用于编程和重新编程低功率，多状态电子保险丝（电子保险丝）的电路结构和方法

    公开(公告)号：WO2011002612A3

    公开(公告)日：2011-03-10

    申请号：PCT/US2010038934

    申请日：2010-06-17

    Applicant: IBM ,  ABOU-KHALIL MICHEL J ,  LEE TOM C ,  LI JUNJUN ,  GAUTHIER ROBERT J JR ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK

    Inventor： ABOU-KHALIL MICHEL J ,  LEE TOM C ,  LI JUNJUN ,  GAUTHIER ROBERT J JR ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK

    IPC: H01L21/82 ,  H01L27/02

    CPC classification number: G11C17/16 ,  G11C11/5692 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/14 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse (150) has two short high atomic diffusion resistance conductor layers (110, 130) positioned on opposite sides (121, 122) and at a same end (123) of a long low atomic diffusion resistance conductor layer (120). A voltage source (170) is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals (first terminal = 170/161/110; second terminal = 170/162/130; third terminal = 170/163/proximate end 123 of conductor layer 120; and, fourth terminal = 170/164/distal end 124 of conductor layer 120) in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces (125, 126). The formation of such opens and/or shorts can be used to achieve different programming states (11, 01, 10, 00). Other circuit structure embodiments incorporate e-fuses (650) with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

    Abstract translation: 公开了电子熔丝编程/重新编程电路的实施例。 在一个实施例中，电子熔丝（150）具有两个短的高原子扩散电阻导体层（110,130），其位于长的低原子扩散电阻导体（110,130）的相对侧（121,122）上和同一端（123） 层（120）。 使用电压源（170）来改变施加到端子（第一端= 170/161/110;第二端= 170/162/130;第三端= 170/163 / 以控制导体层120的近端123;以及导体层120的第四端子= 170/164 /远端124），以便控制长导体层内电子的双向流动，从而形成开路和/或短路 在长导体层 - 短导体层界面（125,126）处。 这种开路和/或短路的形成可以用来实现不同的编程状态（11,01,10,00）。 其他电路结构实施例将e熔丝（650）与额外的导体层和额外的端子结合，以允许更多的编程状态。 还公开了相关联的电子熔丝编程和重新编程方法的实施例。

    AUF MANIPULATION REAGIERENDE BAUGRUPPE MIT STRUKTURMATERIAL IN EINEM ABGEDICHTETEN INNENRAUM
    8.
    发明专利
    AUF MANIPULATION REAGIERENDE BAUGRUPPE MIT STRUKTURMATERIAL IN EINEM ABGEDICHTETEN INNENRAUM 未知

    公开(公告)号：DE102021129176A1

    公开(公告)日：2022-06-15

    申请号：DE102021129176

    申请日：2021-11-10

    Applicant: IBM

    Inventor： ZHANG HONGQING ,  BUNT JAY A ,  LI SHIDONG ,  SONG ZHIGANG ,  LI JUNJUN ,  LIAN GUODA

    IPC: H05K7/14 ,  G08B13/20 ,  H05K1/02

    Abstract: Auf Manipulation reagierende Baugruppen werden bereitgestellt, die eine Leiterplatte, eine an der Leiterplatte angebrachte Gehäusebaugruppe und einen Drucksensor umfassen. Die Leiterplatte enthält eine elektronische Komponente, und die Gehäusebaugruppe ist so mit der Leiterplatte verbunden, dass sie die elektronische Komponente in einem sicheren Volumen einschließt. Die Gehäusebaugruppe umfasst ein Gehäuse mit einem abgedichteten Innenraum und ein Strukturmaterial innerhalb des abgedichteten Innenraums des Gehäuses. Das Strukturmaterial innerhalb des Gehäuses verhindert ein Verformen des Gehäuses aufgrund einer Druckdifferenz zwischen dem Druck des abgedichteten Innenraums und dem zumindest teilweisen Druck um das Gehäuse herum. Der Drucksensor erfasst den Druck im abgedichteten Innenraum des Gehäuses, um es zu ermöglichen, eine Druckänderung zu erkennen, die auf ein Manipulationsereignis hinweist.

    Circuit structure and method for programming and re-programming a low power, multiple states, electronic fuse(E-fuse)
    9.
    发明专利
    Circuit structure and method for programming and re-programming a low power, multiple states, electronic fuse(E-fuse) 未知

    公开(公告)号：GB2483612B

    公开(公告)日：2013-07-10

    申请号：GB201200546

    申请日：2010-06-17

    Applicant: IBM

    Inventor： ABOU-KHALIL MICHEL J ,  LEE TOM C ,  GAUTHIER JR ROBERT J ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK ,  LI JUNJUN

    IPC: H01L21/82 ,  H01L27/02

    Abstract: In one embodiment of an e-fuse programming/re-programming circuit, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

    Bi-Directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures
    10.
    发明专利
    Bi-Directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures 未知

    公开(公告)号：GB2497704A

    公开(公告)日：2013-06-19

    申请号：GB201306287

    申请日：2011-09-14

    Applicant: IBM

    Inventor： ABOU-KHALIL MICHEL J ,  GAUTHIER JR ROBERT J ,  LEE TOM C ,  LI JUNJUN ,  MITRA SOUVICK ,  PUTNAM CHRISTOPHER S

    IPC: H01L27/02

    Abstract: Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode (10a) of a first of the back-to-back stacked SCR (10) is connected to an input (30). An anode (20a) of a second of the back-to-back stacked SCR (20) is connected to ground (GND). Cathodes (10b, 20b) of the first and second of the back- to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes (Di, D2) directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes (D3, D4) of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.

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