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    COMPUTER CONTROL UNIT DEVICE FOR CONTROLLING COERCED OPERATIONS
    2.
    发明专利
    COMPUTER CONTROL UNIT DEVICE FOR CONTROLLING COERCED OPERATIONS 未知

    公开(公告)号：DE3072139D1

    公开(公告)日：1989-02-02

    申请号：DE3072139

    申请日：1980-08-12

    Applicant: IBM

    Inventor： BAZLEN DIETER DR ,  BOCK DIETRICH ,  GETZLAFF KLAUS J ,  HAJDU JOHANN ,  PAINKE HELMUT

    IPC: G06F9/48 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/46

    Abstract: In executing and controlling internal data flow for a particular program, it is often necessary to delay execution of an instruction by the insertion of an appropriate number of wait cycles. Thus, it may be necessary to interrupt instruction execution, for example, to insert a given number of wait cycles for channel access to common storage of the data processing system, for reloading a data or instruction buffer, or for a like situation. In such cases, the control unit has to ignore the particular instruction awaiting execution and execute another forced operation instead. An appropriate code is provided for a NO OPERATION instruction, say all bits zero. When a forced operation is to be executed, this code can be generated with fewer logic means at the output of the instruction register. As a result, there are no control signals active at the output of the decoder. The signals indicating forced operations have to be considered by the decoder only if a control signal is to be generated. If the control signals need be grouped for physical reasons, it is possible to determine which of these signals are a function of forced operations. This will negate the need to otherwise distribute these control signals throughout the decoder, thereby reducing and simplifying the wiring required.

    3.
    发明专利
    未知

    公开(公告)号：DE1499727A1

    公开(公告)日：1972-04-13

    申请号：DE1499727

    申请日：1966-10-12

    Applicant: IBM DEUTSCHLAND INTERNAT BUERO

    Inventor： HOWARD OTTAWAY GERALS ,  PAINKE HELMUT ,  SCHELER TITUS ,  WILL HELMUT ,  VAUGHN WRIGHT WILLIAM

    IPC: G06F9/26 ,  G06F9/00

    Abstract: 1,105,394. Data storage: micro-programme control arrangements. INTERNATIONAL BUSINESS MACHINES CORPORATION. 31 Aug., 1966 [22 Oct., 1965], No. 38738/66. Heading G4A. Certain of the data in a storage register associated with a digital electric data store can be maintained from one storage access cycle to another, means being provided responsive to the state of certain other data positions to select which bytes of a next-to-be addressed word in the store are to be moved into the storage register. In digital electric data-storage apparatus wherein each storage word includes as a portion thereof at least a portion of the address of the next succeeding storage word, storage space is saved due to the fact that when dealing with a sequence of storage words located within adjacent areas of the store the common high order address bits are saved from one storage access cycle to the next. The invention has particular application to micro-programme control using read-only stores. In the arrangement shown (Fig. 1), a read only store (ROS) 22 stores 60-bit storage words which are divided into three instruction words A, B, C of 16, 22 and 22 bits each respectively. One only of these words A, B, or C is transferred during any storage access cycle into ROS register 24 the particular one chosen depending on the configuration of bits 16 and 17 in ROS address register (ROSAR) 28, these bits, originating from the previous micro-instruction, being decoded by word select decoder WD SEL DEC 26 (shown in detail in Fig. 2, not shown). In those cases where word A is selected, bits 10 to 15 of ROS REG 24 remain undisturbed to form the high order part of the next address. USE circuit 34 allows optional (programmed) modification of address bits 18-21 of ROS REG 24 before these bits are applied to ROSAR 29. Bits 1-9, forming the order part of the instruction word, are applied to decode circuits 38 in conventional manner. ROS REG 24 is shown in more detail in Fig. 2 (not shown).

    IMPROVEMENTS IN AND RELATING TO DATA PROCESSING SYSTEMS
    6.
    发明专利
    IMPROVEMENTS IN AND RELATING TO DATA PROCESSING SYSTEMS 未知

    公开(公告)号：GB1243160A

    公开(公告)日：1971-08-18

    申请号：GB2225670

    申请日：1970-05-08

    Applicant: IBM

    Inventor： KNAUFT GUNTER ,  KOEDERITZ FRITZ ,  LAMPE HANS HERMANN ,  PAINKE HELMUT ,  REICHL LEOPOLD ,  VACHENAUER ROBERT ,  VOGT EDWIN ,  WEBER HERMANN

    IPC: G06F11/22 ,  G06F11/267 ,  G06F11/273 ,  G06F13/00 ,  G06F13/42

    Abstract: 1,243,160. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 8 May, 1970 [30 May, 1969], No. 22256/70. Heading G4A. A data processing system includes a CPU, ancillary (e.g. I/O) units connected thereto by a ring bus system comprising an address bus and a data bus, and switching means selectively operable in response to a signal indicative of the absence of execution of a programme instruction involving communication between the CPU and the ancillary units, to apply an address of an ancillary unit defined by manually settable test means to the address bus, the addressed unit supplying data via the data bus to the CPU. The switching means only operates in response to the signal in this way if a manual mode switch is set to "I/O display", the data sent to the CPU being sense data which is displayed on lamps on the CPU control panel. If the mode switch is set to "I/O status stop", then in the presence of the "signal" mentioned above, the machine stops (i.e. at the address defined by the manually settable test means) when the contents of the data bus equal the setting of further manual switches. When test and maintenance work as above is not being performed, the manually settable test means and the further manual switches are used as conventional address and data configuration switches, and the lamps are used for displaying register and storage contents.

    9.
    发明专利
    未知

    公开(公告)号：DE1499722B1

    公开(公告)日：1972-05-25

    申请号：DE1499722

    申请日：1966-10-11

    Applicant: IBM DEUTSCHLAND

    Inventor： HOWARD OTTAWAY GERALD ,  PAINKE HELMUT ,  RAGLAND THOMAS ,  SCHELER TITUS ,  WILL HELMUT ,  VAUGHN WRIGHT WILLIAM

    IPC: G06F9/26 ,  G06F9/20

    Abstract: 1,107,486. Microprogramming. INTERNATIONAL BUSINESS MACHINES CORPORATION. 25 Aug., 1966 [22 Oct., 1965], No. 38140/66. Heading G4A. Bits from a stored word are subjected to a variable logical operation to get the address of the next word. An address applied to a computer microprogramme read-only store controls three decoders. The first two decoders select a word location in the store and the third decoder selects and passes to a register one of three portions of the word as the next micro-instruction. Either of two of the portions fills the register but the third leaves a part of the register unchanged. The next store address is obtained from sections of said register, said " part " of the register feeding the second decoder, another part feeding the third decoder, and a third part being applied to the first decoder via a " use " circuit which either passes the third part unchanged, or AND's or OR's or EXCL-OR's the bits of the third part with corresponding bits from one of a number of working registers in the computer. What the " use " circuit does to the third part is controlled by other bits from the current microinstruction.

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