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    MEMORY CELL COMPRISING A FLOATING GATE DEVICE
    2.
    发明专利
    MEMORY CELL COMPRISING A FLOATING GATE DEVICE 未知

    公开(公告)号：DE3279356D1

    公开(公告)日：1989-02-16

    申请号：DE3279356

    申请日：1982-08-25

    Applicant: IBM

    Inventor： COOK HERBERT CARL ,  TROUTMAN RONALD ROY

    IPC: G11C17/00 ,  G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

    Abstract: A memory system is provided wherein extended injection-limited programming techniques attain a substantially uniform programming behavior from an ensemble of fabricated devices or cells to provide the maximum obtainable voltage threshold shift within a minimum time period. in order to produce these desired results, a floating gate (FG) of a device (10A') is charged by applying to the control gate (CG) of the device a first voltage during a portion of this time period which produces an accelerating field in a dielectric layer disposed adjacent to the floating gate (FG) and then applying to the control gate (CG) during the remaining portion of this time period a second voltage of greater magnitude than that of the first voltage prior to or when the accumulation of charge on the floating gate causes a retarding field to be established in the dielectric layer.

    METHOD OF MAKING COMPLEMENTARY TRANSISTOR METAL OXIDE SEMICONDUCTOR STRUCTURES
    4.
    发明专利
    METHOD OF MAKING COMPLEMENTARY TRANSISTOR METAL OXIDE SEMICONDUCTOR STRUCTURES 未知

    公开(公告)号：DE3372150D1

    公开(公告)日：1987-07-23

    申请号：DE3372150

    申请日：1983-10-21

    Applicant: IBM

    Inventor： GEIPEL HENRY JOHN ,  TROUTMAN RONALD ROY ,  WURSTHORN JOHN MICHAEL

    IPC: H01L27/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L21/82

    Abstract: A process is provided which forms a bulk CMOS structure by initially depositing an oxidation barrier layer (38) on an N type semiconductor substrate (12), which is finally used as gate dielectric, forming a P well (22) in the substrate (12) through a given segment of the barrier layer (38), removing a first segment of the barrier layer to form N+ regions (26, 28) for N channel source and drain, removing a second segment of the barrier layer (38) to form a P+ field region (51, 48), removing a third segment of the barrier layer (38) to form P+ regions (60, 62) for source and drain of a P channel device, forming a first control electrode (68) having a given work function for the P channel device which acts as an ion barrier and then forming a second control electrode (70) between the N channel source and drain regions having a work function different from that of the first control electrode.

    5.
    发明专利
    未知

    公开(公告)号：DE3581852D1

    公开(公告)日：1991-04-04

    申请号：DE3581852

    申请日：1985-06-24

    Applicant: IBM

    Inventor： COTTRELL PETER EDWIN ,  CRAIG WILLIAM JAMES ,  TROUTMAN RONALD ROY

    IPC: H01L27/08 ,  H01L21/761 ,  H01L27/02 ,  H01L27/092

    Abstract: The overvoltage protection circuit, when used with CMOS circuits, protects them from overvoltage conditions while minimizing latch-up conditions in the structure. It consists of a well region (16) of an opposite conductivity to that of the substrate (10, 12) defining a pocket region (18) having a conductivity type which is similar to that of the substrate (10, 12). A first PN junction diode (34) is formed in a portion of the well region (16) and a second PN junction diode (32) is formed in the pocket region (18). The two diodes have opposite polarity and they both are connected to a signal line in such a way that one of the two diodes will be forward biased if the voltage on the signal line exceeds the bounds of the power supply voltages. The pocket region (18) is connected to a Vss terminal which is normally grounded and the well region (16) is connected to a power supply VDD. The doping concentration in the well region (16) is predetermined to have a gradient so that minority carriers injected from one of the diodes in the well region will be repulsed and prevented from moving into the substrate region where they would be majority carriers and they could cause latch-up in the structure or at the very least adversely affect the voltage level of the substrate. Instead the injected carriers recombine in the well region (16) or are collected by the adjacent isolated pocket region (18). … When the second diode (32) is forward biased, the minority carriers are injected into the isolated pocket region (18) and are prevented from reaching the substrate (10) by the underlying well region (14). This prevents these carriers from affecting the operation of adjacent circuits.

    7.
    发明专利
    未知

    公开(公告)号：DE2320420A1

    公开(公告)日：1974-01-17

    申请号：DE2320420

    申请日：1973-04-21

    Applicant: IBM

    Inventor： TROUTMAN RONALD ROY

    IPC: H01L27/04 ,  H01L21/00 ,  H01L21/3205 ,  H01L21/339 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L27/148 ,  H01L29/00 ,  H01L29/417 ,  H01L29/49 ,  H01L29/762 ,  H01L1/14

    Abstract: 1425864 Semiconductor devices INTERNATIONAL BUSINESS MACHINES CORP 30 May 1973 [30 June 1972] 25830/73 Heading H1K In the manufacture of a semiconductor device including spaced conductive lines 44A, B, C constituted by strips of doped semiconductor material, a first non-conductive semiconductor layer 14, e.g. of polycrystalline Si, is deposited on a substrate which may comprise a SiO 2 film 12 on a p type monocrystalline Si body 10. A patterned mask 15A, B, C, D, e.g. of photo-etched silicon nitride, is provided on the layer 12 and a second non-conductive semiconductor layer 24, e.g. of polycrystalline Si, is deposited thereon. In the arrangement shown in Fig. 2 the layer 24 also fills two openings etched through the layers 14 and 12 to the body 10. Parts of the layers 24 and 15 may now be removed to leave patterns as in Fig. 4, and a dopant such as As or P is diffused or ion implanted into the remaining parts 44A-F of the layer 24 and also into the portions of the layer 14 not protected by the retained portion of the mask 15A, B, C, D. In the embodiment doped regions 36, 37 are simultaneously formed in the body 10. The resulting structure comprises a charge-coupled device having spaced conductive phase lines, and an IGFET having source and drain regions 36, 37 connected to conductors 44D, F, and a polycrystalline Si gate electrode 44E. The structure may be sealed in a layer of pyrolytic oxide.

    8.
    发明专利
    未知

    公开(公告)号：DE3584757D1

    公开(公告)日：1992-01-09

    申请号：DE3584757

    申请日：1985-09-03

    Applicant: IBM

    Inventor： KINNEY WAYNE IRVING ,  KOBURGER CHARLES WILLIAM ,  LASKY JEROME BRETT ,  NESBIT LARRY ALAN ,  WHITE FRANCIS ROGER ,  TROUTMAN RONALD ROY

    IPC: H01L27/08 ,  H01L21/033 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/82 ,  H01L21/00

    Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells (26, 28) to each other and also of the field isolation doping regions (32, 10) to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks (30) for subsequent formation of the field-doping regions (32, 10); and a dopant-transmitter during the ion-implanation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers (32, 10) self-aligned to the wells (26, 28) so that, with a subsequent masking step, oxide field isolations (36, 38) are defined over the doped oxide layers (32, 10). A heat cyde is then used to drive the field dopants into the corresponding field-doping regions (40, 42).

    9.
    发明专利
    未知

    公开(公告)号：DE3478175D1

    公开(公告)日：1989-06-15

    申请号：DE3478175

    申请日：1984-02-20

    Applicant: IBM

    Inventor： ELLIS WAYNE FREDERICK ,  GRIFFIN WILLIAM ROBERT ,  TROUTMAN RONALD ROY

    IPC: H03K19/0948 ,  H03K17/06 ,  H03K17/687 ,  H03K19/017 ,  H03K5/02

    Abstract: A driver or pull up circuit is provided which includes a pull up transistor (T5) of a given conductivity type and a precharged bootstrap capacitor (CB) which discharges fully through a second transistor (T3) having a conductivity type opposite to that of the pull up transistor to the control gate or electrode of the pull up transistor. A further transistor (T1) may be used to initiate discharge by providing power supply voltage to the control gate of the pull up transistor.

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