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公开(公告)号：JPH11354724A
公开(公告)日：1999-12-24
申请号：JP33881398
申请日：1998-11-30
Applicant: IBM
Inventor： FRECH ROLAND DR , KLINK ERICH , SHUTLER WILLIAM , WEISS ULRICH , WINKEL THOMAS-MICHAEL
Abstract: PROBLEM TO BE SOLVED: To reduce power noise by connecting a first low pass filter which has an off-chip capacitance and filtrates intermediate-frequency power noise, and a second low pass filter which has an on-chip capacitance and filtrates high-frequency power noise in series. SOLUTION: A first low pass filter which filtrates intermediate-frequency power noise having a frequency of 10-100 MHz is composed of an off-chip capacitance 2, an on-chip resistor R16 which connects a voltage surface VDD to an in-chip node 18, and thin film wiring 8 in the uppermost layer of a multilayered thin film. A second low pass filter which filtrates high-frequency power noise is composed of an on-chip capacitance 12 and an on-chip resistor 7. The first and second low pass filters are connected in series. The first low pass band stage backs up the low induced charge of the capacitance 12 of the second low pass filter and the second low pass band stage becomes the low induced current source of a voltage-controlled device.
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公开(公告)号：DE3377441D1
公开(公告)日：1988-08-25
申请号：DE3377441
申请日：1983-09-15
Applicant: IBM DEUTSCHLAND , IBM
Inventor： BORTZEL MARTIN , LUDWIG REINHOLD , SCHMITS WILHELM , WEISS ULRICH
Abstract: The ocurcurrent protection circuit (10) is used for protecting the switching transistors (Q1,Q2), by disconnecting the driver pulses for the latter upon a critical current value (Ic) being reached. A further protection stage (14) prevents the driver pulses for the switching transistors (Q1,W2) being reinstated for a timed duration upon the increased overload. The initial disconnection stage (12) responding immediately and the further protection stage (14) with a delayed action are both controlled directly via the primary current, i.e. the emitter current (I1,I2) through the conductive switching transistor (Q1, Q2).
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公开(公告)号：GB2509375A
公开(公告)日：2014-07-02
申请号：GB201319714
申请日：2013-11-08
Applicant: IBM
Inventor： HARPER HUBERT , DREPS DANIEL , FERRAIOLO FRANK , WEBEL TOBIAS , WEISS ULRICH , TONG CHING-LUNG L , MAK PAK-KIN
Abstract: A method for clock domain crossing is disclosed, where data is transferred from a first clock domain 160 to a second clock domain 170, wherein the second clock domain has a fixed clock frequency and the first clock domain has a variable clock frequency; the variable frequency being equal to or lower than the fixed frequency. The method comprises writing the data from the first clock domain into two buffers 110/120 connected in parallel with each other. The buffers both have time delays when transferring data from the first clock domain to the second, the time delay of the second buffer being longer than the time delay of the first buffer. The data is forwarded from the first buffer to the second clock domain when the variable frequency is equal to the fixed frequency (when in a synchronous mode), and the data is forwarded from the second buffer to the second clock domain when the variable frequency is lower than the fixed frequency (when in an asynchronous mode). The buffers may be first-in-first-out (FIFO) buffers.
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公开(公告)号：DE19848743A1
公开(公告)日：1999-06-17
申请号：DE19848743
申请日：1998-10-22
Applicant: IBM
Inventor： FRECH ROLAND DR , KLINK ERICH , SHUTLER WILLIAM , WEISS ULRICH , WINKEL THOMAS-MICHAEL
Abstract: There is a first low pass stage, containing a capacity (2) outside the chip (4) for picking-up power supply interference voltages, and a second low pass stage with a capacitor (12) on the chip for picking-up HF interference voltages, with the two stages in series. The first stage capacity and chip are coupled by a thin-film wiring (8). The first stage provides a low-inductance supply for the second stage capacity, while the second stage provides a low-inductance current source for the voltage controlled component.
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公开(公告)号：GB2509375B
公开(公告)日：2014-12-10
申请号：GB201319714
申请日：2013-11-08
Applicant: IBM
Inventor： HARPER HUBERT , DREPS DANIEL , FERRAIOLO FRANK , WEBEL TOBIAS , WEISS ULRICH , TONG CHING-LUNG L , MAK PAK-KIN
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Patent Agency Ranking
公开(公告)号：GB2457147A
公开(公告)日：2009-08-12
申请号：GB0900800
申请日：2009-01-19
Applicant: IBM
Inventor： HESS THOMAS , CAUTILLO GIOVANNI , WEISS ULRICH , ANDRES MICHAEL
IPC: G06F11/14
Abstract: Data is written by a master device to a slave device using an I2C bus and then read back to verify that there were no transmission errors. The data may be transferred from a command register 21 on the master into one or more staging registers 23 on the slave, read back from the staging registers and verified by the master. If the data is successfully verified, the master may send a commit command 24 to cause the slave to transfer the data to the corresponding device register 22. After the data is processed, the master may send a copy back command 25 to copy the data back to the staging register. The master may then read the data once more and verify that it is still valid.
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公开(公告)号：DE69123725T2
公开(公告)日：1997-06-12
申请号：DE69123725
申请日：1991-04-30
Applicant: IBM
Inventor： WEISS ULRICH , KNAUFT GUENTER , SCHMUNKAMP DIETMAR DIPL ING , LEPPLA BERND DIPL ING
IPC: H03K5/15
Abstract: An electrical circuit is described for generating clock pulses for a multi-chip computersystem which contains a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clocksplitter circuit is provided on the clock generation circuit. This clocksplitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clocksplitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clocksplitter, as well as on the skew of the two generated pulse strings. The invention provides an electrical circuit which has an improved throughput time and skew of the generated pulse strings.
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公开(公告)号：DE69123725D1
公开(公告)日：1997-01-30
申请号：DE69123725
申请日：1991-04-30
Applicant: IBM
Inventor： WEISS ULRICH , KNAUFT GUENTER , SCHMUNKAMP DIETMAR DIPL ING , LEPPLA BERND DIPL ING
IPC: H03K5/15
Abstract: An electrical circuit is described for generating clock pulses for a multi-chip computersystem which contains a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clocksplitter circuit is provided on the clock generation circuit. This clocksplitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clocksplitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clocksplitter, as well as on the skew of the two generated pulse strings. The invention provides an electrical circuit which has an improved throughput time and skew of the generated pulse strings.
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公开(公告)号：AT35882T
公开(公告)日：1988-08-15
申请号：AT83109122
申请日：1983-09-15
Applicant: IBM
Inventor： BOERTZEL MARTIN , LUDWIG REINHOLD , SCHMITS WILHELM , WEISS ULRICH
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公开(公告)号：GB2513529A
公开(公告)日：2014-11-05
申请号：GB201220534
申请日：2012-11-15
Applicant: IBM
Inventor： HARRER HUBERT , DREPS DANIEL M , FERRAIOLO FRANK D , WEBEL TOBIAS , WEISS ULRICH , TONG CHING-LUNG L , MAK PAK-KIN
Abstract: A method for clock domain crossing is disclosed, where data is transferred from a first clock domain 160 to a second clock domain 170, wherein the second clock domain has a fixed clock frequency and the first clock domain has a variable clock frequency, the variable frequency being equal to or lower than the fixed frequency. The method comprises writing the data from the first clock domain into two buffers 110/120 connected in parallel with each other. The buffers both have time delays when transferring data from the first clock domain to the second, the time delay of the second buffer being longer than the time delay of the first buffer. The data is forwarded from the first buffer to the second clock domain when the variable frequency is equal to the fixed frequency (when in a synchronous mode), and the data is forwarded from the second buffer to the second clock domain when the variable frequency is lower than the fixed frequency (when in an asynchronous mode). The buffers may be first-in-first-out (FIFO) buffers.
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