公开(公告)号：EP1908076A4

公开(公告)日：2009-06-17

申请号：EP06737703

申请日：2006-03-09

Applicant: IBM

Inventor： HSU LOUIS L C ,  JI BRIAN L ,  LAM CHUNG HON ,  WONG HON-SUM PHILIP

IPC: G11C11/24

CPC classification number: G11C13/0004 ,  G11C15/046

Abstract: A non- volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read- write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit- read-write-search-line, and a drain connected to another end of the second phase change material element.

公开(公告)号：JP2002016255A

公开(公告)日：2002-01-18

申请号：JP2001143342

申请日：2001-05-14

Applicant: IBM

Inventor： COHEN GUY ,  WONG HON-SUM PHILIP

IPC: H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a double-gate integrated circuit and its structure. SOLUTION: The method includes a step for forming a laminated structure, having a channel layer and first insulation layers provided on the respective side surface of the channel layer, a step for forming an opening in the laminated structure, a step for forming source and drain regions in the opening, a step for removing a portion of the laminated structure for leaving a first portion of the channel layer exposed to the external, a step for forming a first gate dielectric layer in the channel layer, a step for forming a first gate electrode in the first gate dielectric layer, a step for removing a portion of the laminated structure to leave a second portion of the channel layer exposed to the external, a step for forming a second gate dielectric layer in the channel layer, a step for forming a second gate electrode in the second gate dielectric layer, and a step for doping the source and drain regions through self-aligned ion implantation. In this case, the first and second gate electrodes are formed independently of each other.

公开(公告)号：BR0308569A

公开(公告)日：2007-04-03

申请号：BR0308569

申请日：2003-02-19

Applicant: IBM

Inventor： COLLINS PHILIP G ,  MARTEL RICHARD ,  WONG HON-SUM PHILIP ,  APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K

IPC: H01L51/30 ,  H01L29/51 ,  H01L51/00 ,  H01L51/05

Abstract: A carbon-nanotube field transistor semiconductor device, comprising: a vertical carbon-nanotube (508) wrapped in a dielectric material (511); a source formed at a first side of the carbon-nanotube; a drain (515) formed on a second side of the carbon-nanotube; a bilayer nitride complex through which a band strap of each of the source and the drain is formed connecting the carbon-nanotube wrapped in the dielectric material to the source and the drain; and a gate (512) formed substantially over a portion of the carbon-nanotube. Further disclosed are methods for forming the following self-aligned carbon-nanotube field effect transistor: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

公开(公告)号：CA2479024A1

公开(公告)日：2003-10-02

申请号：CA2479024

申请日：2003-02-19

Applicant: IBM

Inventor： COLLINS PHILIP G ,  MARTEL RICHARD ,  CHAN KEVIN K ,  WONG HON-SUM PHILIP ,  APPENZELLER JOERG ,  AVOURIS PHAEDON

IPC: H01L51/00 ,  H01L51/05 ,  H01L51/30

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube [104] deposited on a substrate [102], a source a nd a drain [106-107] formed at a first end and a second end of the carbon- nanotube [104], respectively, and a gate [112] formed substantially over a portion of the carbon-nanotube [104], separated from 10 the carbon-nanotube by a dielectric film [111].

公开(公告)号：DE10119411B4

公开(公告)日：2015-06-11

申请号：DE10119411

申请日：2001-04-20

Applicant: IBM

Inventor： COHEN GUY ,  WONG HON-SUM PHILIP

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/786

Abstract: Ein Verfahren, um einen Double-Gate-Transistor herzustellen, wobei – eine laminierte Struktur mit einer Kanalschicht (5) und mit Isolierschichten (1, 2, 3, 6, 7) auf jeder Seite der Kanalschicht (5) gebildet wird; – Öffnungen (8) in der laminierten Struktur gebildet werden; – Drain- und Source-Bereiche (11) in den Öffnungen (8) gebildet werden; – Teile (6, 7) der Isolierschichten (1, 2, 3, 6, 7) über der Kanalschicht (5) entfernt werden, um den ersten Teil einer exponierten Kanalschicht (5) zurückzulassen, wobei – ein erstes Gate-Dielektrikum (15) auf der Kanalschicht (5) gebildet wird; – eine erste Gate-Elektrode (16) auf dem ersten Gate-Dielektrikum (15) gebildet wird; – die Teile (1, 2) der Isolierschichten (1, 2, 3, 6, 7) unter der Kanalschicht (5) und zwischen den beidseits der Kanalschicht (5) angeordneten Drain- und Source-Bereichen (11) entfernt werden, um den zweiten Teil einer exponierten Kanalschicht (5) zurückzulassen, so dass zwischen der Kanalschicht (5) und einer unteren Schicht (3) der Isolierschichten (1, 2, 3, 6, 7) ein Tunnel (20) gebildet wird; – wobei ein zweites Gate-Dielektrikum (21) auf dem zweiten Teil der exponierten Kanalschicht (5) gebildet wird; – eine zweite Gate-Elektrode (22) auf dem zweiten Gate-Dielektrikum (21) gebildet wird; – die Drain- und Source-Bereiche (11) dotiert werden, wobei die erste Gate-Elektrode (16) und die zweite Gate-Elektrode (22) unabhängig voneinander gebildet werden.

公开(公告)号：AT551734T

公开(公告)日：2012-04-15

申请号：AT03721349

申请日：2003-02-19

Applicant: IBM

Inventor： APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN ,  COLLINS PHILIP ,  MARTEL RICHARD ,  WONG HON-SUM PHILIP

IPC: H01L51/05 ,  B82Y10/00 ,  H01L51/00 ,  H01L51/30

Abstract: A carbon-nanotube field transistor semiconductor device, comprising: a vertical carbon-nanotube (508) wrapped in a dielectric material (511); a source formed at a first side of the carbon-nanotube; a drain (515) formed on a second side of the carbon-nanotube; a bilayer nitride complex through which a band strap of each of the source and the drain is formed connecting the carbon-nanotube wrapped in the dielectric material to the source and the drain; and a gate (512) formed substantially over a portion of the carbon-nanotube. Further disclosed are methods for forming the following self-aligned carbon-nanotube field effect transistor: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

公开(公告)号：AU9202401A

公开(公告)日：2002-04-08

申请号：AU9202401

申请日：2001-09-27

Applicant: IBM

Inventor： CHU JACK OON ,  EMIC CHRISTOPHER D ,  HUANG LIJUAN ,  OTT JOHN ALBERT ,  WONG HON-SUM PHILIP

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/778 ,  H01L29/786 ,  H01L29/812

Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, implanting hydrogen into a selected Si1-yGey layer to form a hydrogen-rich defective layer, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and separating two substrates at the hydrogen-rich defective layer. The separated substrates may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC.

公开(公告)号：IE20010380A1

公开(公告)日：2002-02-20

申请号：IE20010380

申请日：2001-04-18

Applicant: IBM

Inventor： COHEN GUY ,  WONG HON-SUM PHILIP

IPC: H01L21/336 ,  H01L29/786 ,  H01L27/01 ,  H01L27/12 ,  H01L29/76

Abstract: A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated structure to leave a first portion of the channel layer exposed, forming a first gate dielectric layer on the channel layer, forming a first gate electrode on the first date dielectric layer, removing portions of the laminated structure to leave a second portion of the channel layer exposed, forming a second gate dielectric layer, doping the drain and source regions, using self-aligned ion implantation, wherein the first gate electrode and the second gate electrode are formed independent of each other.

公开(公告)号：DE10119411A1

公开(公告)日：2001-11-29

申请号：DE10119411

申请日：2001-04-20

Applicant: IBM

Inventor： COHEN GUY ,  WONG HON-SUM PHILIP

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/78

Abstract: The device has a channel region, a first gate above the channel region, a second gate below the channel region, whereby the gates are electrically mutually isolated. The first gate can have a different doping concentration from the second gate. The first gate can have a different doping material from the second gate. Gate dielectrics can be arranged below the first gate and above the second gate. Independent claims are also included for the following: a semiconducting chip with at least one transistor and a method of forming a transistor.

公开(公告)号：SG66410A1

公开(公告)日：1999-07-20

申请号：SG1997004059

申请日：1997-11-14

Applicant: IBM

Inventor： SOLOMON PAUL MICHAEL ,  WONG HON-SUM PHILIP

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/786 ,  H01L21/86 ,  H01L27/088

Abstract: The present invention concerns single-gate and double-gate field effect transistors having a sidewall source contact and a sidewall drain contact, and methods for making such field effect transistors. The channel of the present field effect transistors is raised with respect to the support structure underneath and the source and drain regions form an integral part of the channel.