公开(公告)号：JP2001085637A

公开(公告)日：2001-03-30

申请号：JP2000245911

申请日：2000-08-14

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： FURUKAWA TOSHIHARU ,  GRUENING ULRIKE ,  HORAK DAVID V ,  MANDELMAN JACK A ,  RADENS CARL J ,  RUPP THOMAS S

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To obtain a vertical DRAM having a self-aligned word line conductor on the sidewall of a trench by forming a word line conductor having a sidewall aligned with the sidewall of the trench. SOLUTION: A pad nitride is removed selectively depending on the oxide 240 in an STI region 228. A screen oxide is then grown and array region p-well implantation is carried out and an N+ dopant is implanted in order to form a second diffusion region 210. Subsequently, source and drain implantation is carried out in a support region in order to form a diffusion region 288 and an oxide 242 is formed on the sidewalls 219, 233 of a word line conductor 218, 232 and on the sidewall of a support gate. Finally, a bit line conductor 244 of polysilicon is deposited for planarization. Since word line resistance is decreased, a DRAM device having improved performance can be obtained.

公开(公告)号：JP2000277708A

公开(公告)日：2000-10-06

申请号：JP2000073717

申请日：2000-03-16

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK A ,  NESBIT LARRY ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To prevent resistance of an embedded strap of a DRAM cell from changing by the overlapping manner of a deep trench and an active region. SOLUTION: This semiconductor device contains a semiconductor substrate. At least a pair of deep trenches are formed in the substrate. A collar is formed in at least a part of the sidewall of each of the deep trenches. The inside of each of the deep trenches is filled with a trench filler 44. An embedded strap 46 is formed over the whole of each of the deep trenches and covers the upper surfaces of the trench filler 44 and the collar. An insulating region is formed between a a pair of the deep trenches. A trench upper part dielectric region 52 formed in the deep trench, so as to overlap with the embedded strap 46 of each of the deep trenches.

公开(公告)号：WO0201607A3

公开(公告)日：2002-05-23

申请号：PCT/US0120206

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  BERGNER WOLFGANG ,  BRONNER GARY B ,  GRUENING ULRIKE ,  KUDELKA STEPHEN ,  MICHAELIS ALEXANDER ,  NESBIT LARRY ,  RADENS CARL J ,  SCHLOESSER TILL ,  TEWS HEOMUT HORST

IPC: H01L21/8242

CPC classification number: H01L27/10864

Abstract: A method for clearing an isolation collar (5) from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A insulating material is deposited above a node conductor (3) of the storage capacitor. A layer of silicon (9) is deposited over the barrier material. Dopant ions are implanted at an angle (11) into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

Abstract translation: 一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环（5）的方法，同时将隔离套环留在深沟槽的其他表面。 绝缘材料沉积在存储电容器的节点导体（3）的上方。 一层硅（9）沉积在阻挡材料上。 将掺杂离子以角度（11）注入到深沟槽内的沉积硅层中，从而留下沉积的硅，沿着深沟槽的一侧不被植入。 未投影的硅被蚀刻。 隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

公开(公告)号：JP2001044390A

公开(公告)日：2001-02-16

申请号：JP2000209997

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRONNER GARY ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To obtain non-planar type transistor structure by arranging an active transistor device partially on the sidewall of a deep trench in a cell, and aligning the side wall to a first crystal plane with a crystal orientation along the single- crystal axis. SOLUTION: A deep trench accumulation capacitor 10 is formed in a pad 22 and a substrate 24, and a pattern is formed on the pad 22 using a light lithography step. Then, using such a dry etching step as reactive ion etching, a trench 20 is formed to a desired depth in the substrate 24 through the pad 22. Then, an active transistor device is partially provided on a sidewall 32 of the trench 20, and the sidewall 32 is aligned to first crystal planes (001) and (011) with a crystal orientation set along the single-crystal axis.

公开(公告)号：JP2000228504A

公开(公告)日：2000-08-15

申请号：JP2000028340

申请日：2000-02-04

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  LAROSA GIUSEPPE ,  RADENS CARL ,  DIVAKARUNI RAMA ,  GRUENING ULRIKE

IPC: H01L21/76 ,  H01L21/763 ,  H01L21/765 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a dynamic random access memory formed at a semiconductor body comprising individual paired memory cell separated each other by a vertical electric isolation trench and separated from a support circuit. SOLUTION: An isolation trench 20, comprising a side wall, upper part, and lower part, encloses the region of a semiconductor body 10 comprising a memory cell. Thus, the paired memory cell is electrically separated each other, while separated from a support circuit which is not in the enclosed region but contained in the semiconductor body. The isolation trench lower-part is filled with a conductive material 14, which material comprises a side wall part which is at least partially separated from the trench lower-part side wall by a first electric insulator and a lower part electrically connecting to the semiconductor body. The isolation trench upper-part is filled with a second electric insulator.

公开(公告)号：JP2000323684A

公开(公告)日：2000-11-24

申请号：JP2000085406

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  HALLE SCOTT ,  RADENS CARL J ,  JEFFREY J WERSER ,  BEINTNER JOCHEN ,  MANDELMAN JACK A ,  WITTMANN JUERGEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To form a trench capacitor in a semiconductor body. SOLUTION: A trench capacitor 10 and a MOS transistor 9 are provided in a substrate 16 to form a cell 8 of the DRAM, and the cell 8 is separated from adjacent cells by an STI region 28. The capacitor 10 is composed of an insulator 14 enveloping the trench and a first electrode 24 filled with polysilicon 12, is connected to the drain portion 72 through a buried electrode 22, and is insulated from a gate electrode 20 by a dielectric 23. A second electrode 25 is formed in its bottom portion through an insulator 14. A transistor 9 has N-type drain 72 and source 71 in an upper active region 11 of the substrate 16 and operates with a p well as channel.

公开(公告)号：JP2001068672A

公开(公告)日：2001-03-16

申请号：JP2000210075

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： DIVAKARUNI RAMA ,  JEFFREY P GANBINO ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To obtain an improved structure and a production process of semiconductor device, e.g. MOSFET, in which possibility of thermal shrinkage and permeation of boron are reduced. SOLUTION: A sacrificial oxide layer 1 and a polysilicon/silicon nitride film are deposited sequentially on a substrate 2, an opening is made therein by etching (at the part of 5, 15) and ions are implanted in order to suppress hot carriers 11 thus suppressing punch through 8 between source and drain. After it is filled with a gate insulation film 12, a polysilicon layer 14 and a tungsten layer 15, upper part of an implanted part 18 for extending the source-drain is opened by etching, a spacer 19 is formed therein and contact implantation appropriate to P or N type is carried out. Thereafter, a nitride etch barrier layer 20 is formed, a contact region 21 is opened and filled with a polysilicon layer 22.

公开(公告)号：WO0188977A3

公开(公告)日：2002-06-13

申请号：PCT/US0115759

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARARUNI RAMA ,  SRINIVASAN RADHIKA ,  HO HERBERT ,  BEINTNER JOACHEN ,  LI YUJUN ,  LAROSA GIUSEPPE

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/76224

Abstract: A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.

Abstract translation: 提供半导体器件及其制造方法。 在半导体衬底中形成沟槽。 优选在沟槽的表面上形成薄的氧化物衬垫。 氮化物衬垫形成在沟槽中。 电荷被困在氮化物衬垫中。 在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。 优选地，氧化物填充物直接形成在氮化物衬垫上。

公开(公告)号：WO0237542A2

公开(公告)日：2002-05-10

申请号：PCT/US0146921

申请日：2001-11-05

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  KUDELKA STEPHAN

IPC: H01L21/8242 ,  H01L21/00

CPC classification number: H01L27/10867 ,  H01L27/10876

Abstract: A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.

Abstract translation: 形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

公开(公告)号：WO0199186A3

公开(公告)日：2002-10-10

申请号：PCT/US0119658

申请日：2001-06-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KUNKEL GERHARD ,  KOTECKI DAVID ,  PARK YOUNG JIN ,  GUTMANN ALOIS ,  MANDELMAN JACK A

IPC: H01L21/761 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/761

Abstract: A semiconductor device, in accordance with the present invention, includes a doped semiconductor substrate (102) wherein the doping of the substrate has a first conductivity and a device region (110) formed near a surface of the substrate. The device region includes at least one device well. A buried well (104) is formed in the substrate below the device region. The buried well is doped with dopants having a second conductivity. A trench region (124) surrounds the device region and extends below the surface of the substrate to at least the buried well such that the device region is isolated from other portions of the substrate by the buried well and the trench region.

Abstract translation: 根据本发明的半导体器件包括其中衬底的掺杂具有第一导电性的掺杂半导体衬底（102）和形成在衬底的表面附近的器件区（110）。 器件区域包括至少一个器件。 掩埋阱（104）形成在器件区域下方的衬底中。 掩埋阱掺杂具有第二导电性的掺杂剂。 沟槽区域（124）围绕器件区域并且在衬底的表面下方延伸到至少掩埋阱，使得器件区域通过掩埋阱和沟槽区域与衬底的其他部分隔离。