公开(公告)号：DE10305618B4

公开(公告)日：2007-10-11

申请号：DE10305618

申请日：2003-02-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOETSCHKES UDO ,  MOELLER HOLGER ,  ROGALLI MICHAEL ,  REB ALEXANDER ,  TRINOWITZ REINER

IPC: G03F7/20 ,  G03F1/00 ,  G03F1/08 ,  G03F7/00 ,  G03F7/09 ,  G03F7/095

公开(公告)号：DE10356699A1

公开(公告)日：2005-09-08

申请号：DE10356699

申请日：2003-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CRELL CHRISTIAN ,  BAUCH LOTHAR ,  MOELLER HOLGER ,  ZIEBOLD RALF

IPC: G03B27/42 ,  G03F1/00 ,  G03F7/20 ,  G03F9/00

Abstract: Lithography mask having a structure for the fabrication of semiconductor components, in particular memory components, for a direction-dependent exposure device, featuring at least one auxiliary structure ( 1 ) for minimizing scattered light, the auxiliary structure ( 1 ) essentially being arranged in a low-resolution exposure direction of the direction-dependent exposure device ( 11, 11 a, 11 b) for the mask ( 10, 10 a , 10 b). A means for reducing scattered light is thus created by the auxiliary structure in a simple manner.

公开(公告)号：DE10305618A1

公开(公告)日：2004-09-09

申请号：DE10305618

申请日：2003-02-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOETSCHKES UDO ,  MOELLER HOLGER ,  ROGALLI MICHAEL ,  REB ALEXANDER ,  TRINOWITZ REINER

IPC: G03F1/00 ,  G03F1/08 ,  G03F7/00 ,  G03F7/09 ,  G03F7/095 ,  G03F7/20

Abstract: On semiconductor wafer (1) is formed layer (2), whose surface (4) has at least one depression (6). On surface is deposited first photosensitive lacquer (7), filling depression. First lacquer is exposed on surface and above depression, with lacquer in depression not exposed. First lacquer is developed and photosensitive second lacquer (9) is deposited on wafer and is again exposed with structure pattern. First exposition is carried out with radiation doses sufficient to expose surface after development. INDEPENDENT CLAIM is included for use of method in manufacture of semiconductor memory.

公开(公告)号：DE10361875A1

公开(公告)日：2005-07-21

申请号：DE10361875

申请日：2003-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFORR RAINER ,  MUELDERS THOMAS ,  CRELL CHRISTIAN ,  BAUCH LOTHAR ,  ZIEBOLD RALF ,  MOELLER HOLGER ,  GRAESER ANNETT

IPC: G03F1/00 ,  G03F1/36 ,  G03F1/14 ,  G03F1/08

Abstract: A lithography mask comprises a structure for transferring a layout onto a substrate. A blind macrostructure (1) is used to suppress scattered light, and is located at a bright region of the structure. The macrostructure is partially transparent and does not print on the substrate or form a resist structure.

公开(公告)号：DE102004022016B4

公开(公告)日：2006-04-20

申请号：DE102004022016

申请日：2004-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOELLER HOLGER ,  GENZ OLIVER

IPC: G03F7/38

Abstract: A process for forming a pattern in a layer on a semiconductor substrate (1) comprises applying a photo sensitive resist to the substrate, exposing primary and secondary sections of the resist, and heating the exposed resist. One section of the resist is heated to a first temperature and the other section is heated to a second temperature. The heated resist is then developed and the substrate is etched to transfer the openings and remove the developed resist.

公开(公告)号：DE102004022016A1

公开(公告)日：2005-12-08

申请号：DE102004022016

申请日：2004-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOELLER HOLGER ,  GENZ OLIVER

IPC: G03F7/38

Abstract: A process for forming a pattern in a layer on a semiconductor substrate (1) comprises applying a photo sensitive resist to the substrate, exposing primary and secondary sections of the resist, and heating the exposed resist. One section of the resist is heated to a first temperature and the other section is heated to a second temperature. The heated resist is then developed and the substrate is etched to transfer the openings and remove the developed resist.

公开(公告)号：DE10338503B3

公开(公告)日：2005-05-25

申请号：DE10338503

申请日：2003-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOELLER HOLGER ,  VOIGT INA ,  KOWALEWSKI JOHANNES ,  HEINECK LARS

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

Abstract: The method involves providing a hard mask layer (5a,5b) on a semiconductor substrate (1), providing a structured mask layer (10') on the hard mask layer, carrying out at least one inclined ion implantations so that an implanted region (5b) lies at least partly under the structured mask layer and a non-implanted region (5a) under the structured layer is smaller than corresponding region of the structured layer, removing the structured layer and structuring the hard mask layer by selectively removing the non-implanted region or the implanted region by etching.