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    DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURE OF THE SAME
    1.
    发明专利
    DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURE OF THE SAME 失效

    公开(公告)号：JP2000196045A

    公开(公告)日：2000-07-14

    申请号：JP37569999

    申请日：1999-12-28

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： RADENS CARL ,  GRUENING ULRIKE ,  DEBROSSE JOHN ,  MANDELMAN JACK

    IPC: H01L29/78 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To obtain necessary insulation between a capacitor for storage and a transistor in a memory cell, using both a capacitor for storage in a vertical trench and a vertical transistor. SOLUTION: One memory cell formed in a semiconductor main body 10 includes a polycrystalline silicon packing part 22 as a capacitor for storage and one field-effect transistor. This field-effect transistor includes a source 43 formed in the sidewall of a trench, a drain 42 formed in the semiconductor main body and provided with a surface in common with the upper face of the semiconductor main body, a channel region including both vertical and horizontal parts, and a polycrystalline silicon gate at the upper part of the trench. Thus, an insulating oxide layer 28 at the top end of the polycrystalline silicon packing part, which is useful as a storage node and the polycrystalline silicon packing part which is useful as a gate conductor can be obtained in this process for manufacturing.

    EMBEDDED VERTICAL DRAM CELLS AND DUAL WORKFUNCTION LOGIC GATES
    2.
    发明申请
    EMBEDDED VERTICAL DRAM CELLS AND DUAL WORKFUNCTION LOGIC GATES 审中-公开
    嵌入式垂直DRAM电池和双功能逻辑门

    公开(公告)号：WO0245130A3

    公开(公告)日：2004-01-08

    申请号：PCT/US0144625

    申请日：2001-11-28

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

    IPC: H01L27/10 ,  H01L21/8242

    CPC classification number: H01L27/10894 ,  H01L27/10864 ,  H01L27/10885 ,  H01L27/10891

    Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports, comprising: Forming a french capacitor in a silicon substrate having a gate oxide layer, a polysilicon layer, and a top dialectric nitride layer deposited thereon; Applying a patterned mask over the array and support areas and forming recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Forming a silicide and oxide cap in the recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Applying a block mask to protect the supports while stripping the nitride layer from the array and etching the exposed polysilicon layer to the top of the gate oxide layer; Striping the nitride layer from the support region and depositing a polysilicon layer over the array and support areas; Applying a mask to pattern and form a bitline diffusion stud landing pad in the array and gate conductors for the support transistors; Saliciding the tops of the landing pad and the gate conductors; Applying an interlevel oxide layer and then opening vias in the interlevel oxide layer for establishing conductive wiring channels.

    Abstract translation: 一种用于生产非常高密度的嵌入式DRAM /非常高性能的逻辑结构的方法，包括在支撑体中制造具有水银源/漏极和栅极导体双功函数MOSFET的垂直MOSFET DRAM单元，包括：在硅衬底中形成法兰电容器， 栅极氧化物层，多晶硅层和沉积在其上的顶部侧面氮化物层; 在阵列和支撑区域上施加图案化掩模并在氮化物层，多晶硅层和浅沟槽隔离区域中形成凹陷; 在氮化物层，多晶硅层和浅沟槽隔离区域的凹槽中形成硅化物和氧化物盖; 施加阻挡掩模以保护支撑物，同时从阵列剥离氮化物层并将暴露的多晶硅层蚀刻到栅极氧化物层的顶部; 从支撑区域剥离氮化物层并在阵列和支撑区域上沉积多晶硅层; 应用掩模来图案化并在阵列中形成位线扩散螺柱着陆焊盘，并在支撑晶体管上形成栅极导体; 打击着陆板和门导体的顶部; 施加层间氧化层，然后在层间氧化层中开通通孔，以建立导电布线通道。

    TRENCH CAPACITOR DRAM PROCESS WITH PROTECTED TOP OXIDE DURING STI ETCH
    3.
    发明申请
    TRENCH CAPACITOR DRAM PROCESS WITH PROTECTED TOP OXIDE DURING STI ETCH 审中-公开
    在STI蚀刻期间具有保护的顶部氧化物的TRENCH电容器DRAM工艺

    公开(公告)号：WO0231878A3

    公开(公告)日：2002-10-31

    申请号：PCT/US0126644

    申请日：2001-08-24

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： JAIPRAKASH VENKATACHALAN ,  MANDELMAN JACK ,  DIVAKARUNI RAMACHANDRAR ,  MALIK RAJEEV ,  SEITZ MIHEL

    IPC: H01L21/8242

    CPC classification number: H01L27/10861

    Abstract: An array top oxide is protected in the manufacture of vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic random access memory (DRAM) arrays by a protective etch stop layer (18) which protects the top oxide (16) and prevents word line to substrate shorts and/or leakage. Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor polysilicon (17) of the vertical MOSFET to the top surface of the top oxide (16). A thin polysilicon layer (18) is deposited over the planarized surface and an active area (AA) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The AA mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches (20).

    Abstract translation: 在通过保护顶部氧化物（16）的保护性蚀刻停止层（18）制造垂直金属氧化物半导体场效应晶体管（MOSFET）动态随机存取存储器（DRAM）阵列中的阵列顶部氧化物被保护，并且防止字线 衬底短路和/或泄漏。 包括垂直MOSFET阵列的DRAM器件的处理通过将垂直MOSFET的阵列栅极导体多晶硅（17）平坦化到顶部氧化物（16）的顶表面进行。 在平坦化表面上沉积薄多晶硅层（18），并沉积有源区（AA）衬垫氮化物和原硅酸四乙酯（TEOS）堆叠。 使用AA掩模将焊盘层打开到硅表面，并且使用浅沟槽隔离（STI）蚀刻来形成隔离沟槽（20）。

    SELF-LIMITING POLYSILICON BUFFERED LOCOS FOR DRAM TRENCH CAPACITOR COLLAR
    4.
    发明申请
    SELF-LIMITING POLYSILICON BUFFERED LOCOS FOR DRAM TRENCH CAPACITOR COLLAR 审中-公开
    用于DRAM TRENCH电容器COLLAR的自限制多晶硅缓冲电路

    公开(公告)号：WO0195391A8

    公开(公告)日：2002-03-28

    申请号：PCT/US0117927

    申请日：2001-06-01

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： NESBIT LARRY ,  MCSTAY IRENE LENNOX ,  RADENS CARL ,  TEWS HELMUT HORST ,  DIVAKARUNI RAMA ,  MANDELMAN JACK

    IPC: H01L21/8242

    CPC classification number: H01L27/10861 ,  H01L27/10867

    Abstract: A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner (81) is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer (79). A layer of amorphous silicon (83) is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist (83) is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar (89) along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.

    Abstract translation: 一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。 首先在硅衬底中形成DRAM沟槽。 然后，氮化物衬垫（81）沉积在硅沟槽壁上。 氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层（79）上。 然后在氮化物衬垫上沉积一层非晶硅（83）。 在非晶硅的氧化表面上沉积氮化硅层。 在沟槽的下部形成抗蚀剂（83），去除非晶硅顶部的露出的氮化硅层，使非晶硅层的上部露出。 然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环（89）。 非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。 氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。 在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

    DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR
    8.
    发明申请
    DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 审中-公开
    双端口增益电池与侧面和顶部门控读取晶体管

    公开(公告)号：WO2007023011A2

    公开(公告)日：2007-03-01

    申请号：PCT/EP2006063581

    申请日：2006-06-27

    Applicant: IBM ,  IBM UK ,  MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

    Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL ,  WANG GENG

    IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/12

    CPC classification number: H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

    Abstract: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

    Abstract translation: 用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储器单元和工艺序列。 具体而言，本发明提供了与现有SOI CMOS技术兼容的密集，高性能SRAM单元替换。 本领域已知各种增益单元布局。 本发明通过提供用SOI CMOS制造的密集布局来改进现有技术。 一般而言，存储器单元包括分别设置有栅极，源极和漏极的第一晶体管; 第二晶体管，分别具有第一栅极，第二栅极，源极和漏极; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

    METHOD FOR WRAPPED-GATE MOSFET
    10.
    发明公开
    METHOD FOR WRAPPED-GATE MOSFET 审中-公开
    方法包裹的栅极MOSFET

    公开(公告)号：EP1436843A4

    公开(公告)日：2008-11-26

    申请号：EP02780350

    申请日：2002-09-17

    Applicant: IBM

    Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

    IPC: H01L29/41 ,  H01L29/76 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78618

    Abstract: The present invention relates to a wrapped-gate transistor including a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions (28) are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer (40) is formed on the substrate. A gate electrode (42) is formed on the gate dielectric layer (40) to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric (40) therebetween. The substrate is a silicon island (12) formed on an insulation layer of an SOI (silicon-on-insulator) substrate or a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions (28) are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the 'body-to-source' voltage.

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