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公开(公告)号：JP2001229691A
公开(公告)日：2001-08-24
申请号：JP2000374346
申请日：2000-12-08
Applicant: ST MICROELECTRONICS SRL
Inventor： MANSTRETTA ALESSANDRO , MICHELONI RINO , PIERIN ANDREA , YERO EMILIO
Abstract: PROBLEM TO BE SOLVED: To obtain a non-volatile memory device having row redundancy being freely constituted in which correcting capability of architecture can be reconstituted for each chip. SOLUTION: This device comprises a row decoding circuit 12 and a column decoding circuit 13, a circuit reading out stored data in a memory cell and changing it, a memory matrix 14 which can store a fault row address, and a control circuit. The device also comprises a circuit comparing a fault row address stored in the memory matrix 14 with a selected row address in order to recognize a selected row address ADr and perform relieving selection of a fault row and selection of a corresponding redundant cell row at the time of recognizing validness, and configuration register comprising a matrix of a non-volatile memory cell and a control circuit.
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公开(公告)号：JPH11260087A
公开(公告)日：1999-09-24
申请号：JP37435798
申请日：1998-12-28
Applicant: ST MICROELECTRONICS SRL
Inventor： MANSTRETTA ALESSANDRO , PIERIN ANDREA , TORELLI GUIDO
Abstract: PROBLEM TO BE SOLVED: To alleviate a total load by providing a second and a third field effect transistors having the conductivity types same as or opposite to the first field effect transistor, providing a body connecting terminal to the first terminal thereof and then connecting the first terminal of the first transistor to the bias of the memory device. SOLUTION: A row driver includes a source terminal connected to a first drive voltage VBODY, a gate terminal connected to a bias voltage generator G1, a drain terminal connected to an input terminal IN of row driver and a PMOS transistor M1 having the body terminal connected to the source terminal. The row driver also includes a phase inverter I coupled between the input terminal IN and output terminal OUT. M1 is 'on' or 'off' depending on the voltage impressed to the node G1 in regard to the selected word line and M2 bomes 'on' while M3 becomes 'off' in the triode area.
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公开(公告)号：JP2000357396A
公开(公告)日：2000-12-26
申请号：JP2000139757
申请日：2000-05-12
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , MANSTRETTA ALESSANDRO , MICHELONI RINO
Abstract: PROBLEM TO BE SOLVED: To obtain a non-volatile memory having a row redundancy function in which an access time for a memory word is drastically shortened. SOLUTION: In a non-volatile memory device having a memory cell in which rows and columns are arranged and being provided with at least one sector 100 of a matrix cell, a row decoder D and a column decoder decoding an address signal and activating rows and columns respectively, and at least one sector 110 of a redundancy cell, and being able to replace a row of a sector of a matrix cell by a row of a sector of the redundancy cell, the device is provided with a local column decoder J for a sector 100 of a matrix cell and a local column decoder L for a sector 110 of the redundancy cell. Local column decoders L for a matrix cell and for the redundancy cell are controlled by the outside signal so that rows of the sector 110 of the redundancy cell and rows of the sector 100 of a matrix cell are simultaneously activated.
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公开(公告)号：JP2001057091A
公开(公告)日：2001-02-27
申请号：JP2000236205
申请日：2000-08-03
Applicant: ST MICROELECTRONICS SRL
Inventor： TORELLI GUIDO , MODELLI ALBERTO , MANSTRETTA ALESSANDRO
Abstract: PROBLEM TO BE SOLVED: To obtain aprogramming method for a non-volatile memory in which the time required for performing programming operation can be minimized by control of gate voltage. SOLUTION: Threshold voltage in which a value is increased for a pre- programming pulse at the time of programming is applied to a gate terminal of each cell to be programmed, and an increment of threshold voltage of a cell to be programmed is made equal to an increment of gate voltage (ΔVcp). Variation interval of threshold voltage relating to each level is held at a small value to move from one threshold level to a next threshold level, in order to reduce a whole programming time, continuous pulses are supplied to each cell to be programmed with non-verifying until it is reduced to a voltage level to be programmed or less (107-109), and a verifying process (110) is performed, successively, a programming process and a verifying process (112, 110, 117, 118) are continuously performed until a cell to be programmed reaches the desired threshold value.
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公开(公告)号：JP2000067592A
公开(公告)日：2000-03-03
申请号：JP14849699
申请日：1999-05-27
Applicant: ST MICROELECTRONICS SRL
Inventor： MANSTRETTA ALESSANDRO , PIERIN ANDREA , TORELLI GUIDO
Abstract: PROBLEM TO BE SOLVED: To provide a selector switch, integrated monolithically for a device containing an electrically programmable memory cell, which has a simple circuit and operation capability adapted to various use. SOLUTION: Selector switches are integrated monolithically in a circuit of CMOS technology for a memory cell device being electrically programmable and having at least first and second input terminals connecting with first (HV) and second (LV) voltage generators respectively and an output terminal (OUT). First (P1) and second (P2) field effect selection transistors are connected between the first input terminal and the output terminal and the second input terminal and the output terminal respectively through a first and second terminal.
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Patent Agency Ranking
公开(公告)号：DE69901259D1
公开(公告)日：2002-05-16
申请号：DE69901259
申请日：1999-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： MANSTRETTA ALESSANDRO , PIERIN ANDREA , TORELLI GUIDO
Abstract: A monolithically integrated selector for electrically programmable memory cell devices can be switched at an output terminal (OUT) between a high voltage (HV) and a low voltage (LV). It comprises a leg (N2, N1) of fast ground discharge (GND) from the output terminal, a discharge control leg (P1, N3, N4) driving the selector switching through a phase generator (PHG).
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公开(公告)号：DE69516402T2
公开(公告)日：2000-11-02
申请号：DE69516402
申请日：1995-07-31
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , DANIELE VINCENZO , GASTALDI ROBERTO , MANSTRETTA ALESSANDRO , TELECCO NICOLA , TORELLI GUIDO
IPC: G11C11/56
Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2 (n > = 2) different programming levels, provides for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a discrete set of m distinct cell current values (IC0-IC15), each cell current value (IC0-IC15) corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current (IC) with a prescribed number of reference currents (IR1,IR2,IR3) having values comprised between a minimum value and a maximum value of said discrete set of m cell current values (IC0-IC15) and dividing said discrete set of m cell current values (IC0-IC15) in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current (IC) belongs; repeating step a) for the sub-set of cell current values to which the cell current (IC) belongs, until the sub-set of cell current values to which the cell current (IC) belongs comprises only one cell current value, which is the value of the current (IC) of the memory cell (MC) to be sensed.
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公开(公告)号：DE69514783T2
公开(公告)日：2000-06-08
申请号：DE69514783
申请日：1995-03-23
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , DANIELE VINCENZO , GASTALDI ROBERTO , MANSTRETTA ALESSANDRO , TELECCO NICOLA , TORELLI GUIDO
Abstract: A sensing circuit for serial dichotomic sensing of multiple-levels memory cells (MC) which can take one programming level among a plurality of m=2 (n >= 2) different programming levels, comprises biasing means for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a plurality of m distinct cell current values (IC0-IC3), each cell current value (IC0-IC3) corresponding to one of the programming levels, a current comparator (1) for comparing the cell current (IC) with a reference current (IR) generated by a variable reference current generator (G), and a successive approximation register (2) supplied with an output signal (CMP) of the current comparator (1) and controlling the variable reference current generator (G). The variable reference current generator comprises an offset current generator (Ioff) permanently coupled to the current comparator (1), and m-2 distinct current generators (IR0,IR1), independently activatable by the successive approximation register (2), each one generating a current (IC1,IC2) equal to a respective one of the plurality of cell current values (IC0-IC3).
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公开(公告)号：DE69626631T2
公开(公告)日：2003-11-06
申请号：DE69626631
申请日：1996-06-05
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , GASTALDI ROBERTO , MANSTRETTA ALESSANDRO , CAPPELLETTI PAOLO , TORELLI GUIDO
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公开(公告)号：DE69627318D1
公开(公告)日：2003-05-15
申请号：DE69627318
申请日：1996-08-22
Applicant: ST MICROELECTRONICS SRL
Inventor： ROLANDI PAOLO , CALLIGARIO CRISTIANO , MANSTRETTA ALESSANDRO , TORELLI GUIDO
Abstract: In a storage device of the multi-level type, comprising a plurality of memory cells addressable through an address input (RADR,CADR), each cell being adapted for storing more than one binary information element in a MOS transistor which has a control gate, and a floating gate for storing electrons to modify the threshold voltage of the transistor, and comprising a circuit enabling a Direct Memory Access (DMA) mode for directly accessing the memory cells from outside the device, the memory cells are programmed in the direct memory access mode by controlling, from outside the device, the amount of charge stored into the floating gate of each transistor.
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