公开(公告)号：US20010050266A1

公开(公告)日：2001-12-13

申请号：US09847798

申请日：2001-05-02

Inventor： David W. Sherrer ,  Gregory A. Ten Eyck ,  Dan A. Steinberg ,  Neal Ricks

IPC: B29D011/00 ,  G02B006/00

CPC classification number: B81C1/00126 ,  B81B2203/0384 ,  B81C1/00428 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/0178 ,  G02B6/3636 ,  G02B6/3652 ,  G02B6/3692 ,  G02B6/423 ,  G02B2006/12176

Abstract: Methods for making a micromachined device (e.g. an microoptical submount) having positive features (extending up from a device surface) and negative features (extending into the device surface). The present techniques locate the positive feature and negative features according to a single mask step. In one embodiment, a hard mask is patterned on top of the device layer of an SOI wafer. Then, RIE is used to vertically etch to the etch stop layer, forming the positive feature. Then, the positive feature is masked, and metal or hard mask is deposited on the exposed areas of the etch stop layer. Then, portions of the device layer are removed, leaving the patterned metal layer on the etch stop layer. Then, the etch stop layer is removed in an exposed area, uncovering the handle layer. Then, the handle layer is etched in an exposed area to form the negative feature.

Abstract translation: 用于制造具有正特征（从器件表面向上延伸）和负特征（延伸到器件表面）的微加工器件（例如，微光学基座）的方法。 本技术根据单个掩模步骤定位正特征和负特征。 在一个实施例中，在SOI晶片的器件层的顶部上形成硬掩模。 然后，RIE用于垂直蚀刻到蚀刻停止层，形成阳性特征。 然后，正面特征被掩蔽，并且金属或硬掩模沉积在蚀刻停止层的暴露区域上。 然后，去除器件层的部分，留下图案化的金属层在蚀刻停止层上。 然后，在曝光区域中去除蚀刻停止层，露出手柄层。 然后，在曝光区域中蚀刻手柄层以形成负面特征。

公开(公告)号：US5759870A

公开(公告)日：1998-06-02

申请号：US520055

申请日：1995-08-28

Applicant: Weijie Yun ,  Liwei Lin ,  Tariq M. Haniff

Inventor： Weijie Yun ,  Liwei Lin ,  Tariq M. Haniff

IPC: B81B3/00 ,  G01L9/00 ,  H01L21/44 ,  H01L21/465

CPC classification number: B81C1/00047 ,  G01L9/0042 ,  G01L9/0054 ,  G01L9/0055 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C2201/0178 ,  B81C2203/0136

Abstract: Methods for surface micro-machining silicon wafers, including coating cavity sidewalls with oxidation-resistant material to prevent lateral oxidation. This in turn prevents "bird's beak" during formation of a diaphragm. The methods are useful for, among other things, the manufacture of absolute-type pressure sensors. Along with bulk micro-machining techniques, the methods can be used to produce gauge- and differential-type pressure sensors, as well.

Abstract translation: 用于表面微加工硅晶片的方法，包括具有抗氧化材料的涂层腔侧壁以防止侧向氧化。 这反过来又会在隔膜的形成期间阻止“鸟的喙”。 这些方法尤其适用于制造绝对型压力传感器。 随着大量的微加工技术，该方法也可用于生产量规和差压式压力传感器。

公开(公告)号：US20240199415A1

公开(公告)日：2024-06-20

申请号：US18084811

申请日：2022-12-20

Applicant: STMicroelectronics International N.V.

Inventor： Federico VERCESI ,  Andrea NOMELLINI ,  Paolo FERRARI

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00285 ,  B81B7/0038 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0315 ,  B81B2207/07 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2201/0178 ,  B81C2203/0118

Abstract: Disclosed herein is a process flow for forming a MEMS IMU including an accelerometer and a gyroscope each located in a separate sealed cavity maintained at a different pressure. Formation of the MEMS IMU includes the use of a first vHF release to etch a sacrificial layer underneath a structural layer containing the accelerometer and gyroscope and capping the device under formation to set both cavities at a first pressure. The floor of one of the cavities is formed to including a gas permeable layer. Formation further includes forming a chimney underneath the gas permeable layer and then performing a second vHF release to etch through the gas permeable layer and expose the cavity containing the gas permeable layer so that its pressure may be set to be different than that of the other cavity when the chimney is sealed.

公开(公告)号：US11944998B2

公开(公告)日：2024-04-02

申请号：US16822018

申请日：2020-03-18

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Byung Chul Lee ,  Dong-Hyun Kang ,  Jin soo Park ,  Tae Song Kim

IPC: B06B1/02 ,  B81B3/00 ,  B81C1/00

CPC classification number: B06B1/0292 ,  B81B3/0086 ,  B81C1/00698 ,  B81B2201/0271 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C2201/0171 ,  B81C2201/0178 ,  B81C2201/0194

Abstract: A method of fabricating a capacitive micromachined ultrasonic transducer (CMUT) according to one aspect of the present invention may include forming, on a semiconductor substrate, a first region implanted with impurity ions at a first average concentration and a second region implanted with no impurity ions or implanted with the impurity ions at a second average concentration lower than the first average concentration, forming an insulating layer by oxidizing the semiconductor substrate wherein the insulating layer includes a first oxide layer having a first thickness on at least a part of the first region and a second oxide layer having a second thickness smaller than the first thickness on at least a part of the second region, and forming a membrane layer on the insulating layer such that a gap is defined between the second oxide layer and the membrane layer.

公开(公告)号：US20240017989A1

公开(公告)日：2024-01-18

申请号：US18348664

申请日：2023-07-07

Applicant: ROHM CO., LTD.

Inventor： Martin Wilfried HELLER

IPC: B81C1/00 ,  B81B7/02

CPC classification number: B81C1/00166 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81B2203/033 ,  B81B2203/04 ,  B81C2201/0132 ,  B81C2201/0177 ,  B81C2201/019 ,  B81C2201/0178

Abstract: A MEMS device includes a substrate which has a first main surface and a second main surface facing the first main surface, and in which a silicon substrate, a silicon carbide layer having conductivity, and a silicon layer are sequentially stacked from a second main surface side toward a first main surface side, a cavity recessed over the silicon layer, the silicon carbide layer, and the silicon substrate from the first main surface of the substrate to the second main surface side of the substrate, a MEMS electrode which is arranged in the cavity, is composed of the silicon layer and the silicon carbide layer, and is spaced apart from a bottom surface of the cavity to the first main surface side, and an isolation joint which divides the MEMS electrode in a plan view and mechanically connects and electrically isolates both sides of the divided MEMS electrode.

公开(公告)号：US20230348259A1

公开(公告)日：2023-11-02

申请号：US17732467

申请日：2022-04-28

Applicant: Vanguard International Semiconductor Corporation

Inventor： WAI MUN CHONG ,  RAKESH CHAND ,  GUOFU ZHOU ,  ROHIT PULIKKAL KIZHAKKEYIL ,  RAMACHANDRAMURTHY PRADEEP YELEHANKA

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0051 ,  B81C1/00341 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0136 ,  B81B2207/012 ,  B81C2201/0132 ,  B81C2201/0178 ,  B81C2203/0792

Abstract: A micro-electro-mechanical system (MEMS) device includes a supporting substrate, a cavity, a stopper, a MEMS structure, and a bonding dielectric layer. The cavity is located at a top surface of the supporting substrate. The stopper is adjacent to the cavity, where a top surface of the stopper and the top surface of the supporting substrate are on the same level in a height. The MEMS structure is disposed on the supporting substrate, where the MEMS structure includes a proof mass and a suspension beam. The proof mass is disposed directly above the stopper, and the suspension beam is disposed directly above the cavity. The bonding dielectric layer is disposed between the top surface of the supporting substrate and a bottom surface of the MEMS structure.

公开(公告)号：US20190233280A1

公开(公告)日：2019-08-01

申请号：US16213019

申请日：2018-12-07

Applicant: Shenyang Silicon Technology Co., Ltd.

Inventor： Xiang LI

IPC: B81C1/00 ,  B81B1/00

CPC classification number: B81C1/00047 ,  B08B3/08 ,  B32B37/06 ,  B32B38/0008 ,  B32B43/006 ,  B32B2038/0016 ,  B32B2310/14 ,  B32B2313/00 ,  B32B2457/14 ,  B81B1/004 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C1/00357 ,  B81C1/00507 ,  B81C1/00849 ,  B81C2201/0116 ,  B81C2201/0125 ,  B81C2201/0178 ,  B81C2201/019 ,  B81C2201/0192 ,  B81C2201/0194

Abstract: A method for processing a silicon wafer with a through cavity structure. The method is operated in accordance with the following sequence: performing ion implantation on a silicon wafer or pattern wafer; implanting a dummy substrate; bonding the silicon wafer to the pattern wafer; performing grinding and polishing, and thinning the pattern wafer to a depth exposing the pattern; bonding; and peeling the dummy substrate. Compared with the prior art, the present invention is standard in operation, and the product quality can be effectively guaranteed. The product has high cost performance and excellent comprehensive technical effect. The present invention has expectable relatively large economic values and social values.

公开(公告)号：US09656860B2

公开(公告)日：2017-05-23

申请号：US15254828

申请日：2016-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Earl Vedere Atnip ,  Raul Enrique Barreto ,  Kelly J. Taylor

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00666 ,  B81B3/0072 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C1/00365 ,  B81C2201/0108 ,  B81C2201/0132 ,  B81C2201/0167 ,  B81C2201/0178

Abstract: In described examples, a MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first metal layer is exposed to an oxidizing ambient which oxidizes a surface layer of the first metal layer where exposed to the oxidizing ambient, to form a native oxide layer of the first metal layer. A second metal layer is subsequently formed over the native oxide layer of the first metal layer. The sacrificial layer is subsequently removed, forming a released metal structure.

公开(公告)号：US20160368765A1

公开(公告)日：2016-12-22

申请号：US15254828

申请日：2016-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Earl Vedere Atnip ,  Raul Enrique Barreto ,  Kelly J. Taylor

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00666 ,  B81B3/0072 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C1/00365 ,  B81C2201/0108 ,  B81C2201/0132 ,  B81C2201/0167 ,  B81C2201/0178

Abstract: In described examples, a MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first metal layer is exposed to an oxidizing ambient which oxidizes a surface layer of the first metal layer where exposed to the oxidizing ambient, to form a native oxide layer of the first metal layer. A second metal layer is subsequently formed over the native oxide layer of the first metal layer. The sacrificial layer is subsequently removed, forming a released metal structure.

Abstract translation: 在所描述的示例中，通过在衬底上形成牺牲层并在牺牲层上形成第一金属层来形成MEMS器件。 随后，将第一金属层暴露于氧化环境中，氧化暴露于氧化环境的第一金属层的表面层，以形成第一金属层的天然氧化物层。 随后在第一金属层的自然氧化物层上形成第二金属层。 随后去除牺牲层，形成释放的金属结构。

公开(公告)号：US08716050B2

公开(公告)日：2014-05-06

申请号：US13721496

申请日：2012-12-20

Applicant: The Hong Kong University of Science and Technology

Inventor： Man Wong ,  Fan Zeng

IPC: H01L21/00 ,  H01L29/82

CPC classification number: H01L21/461 ,  B01J19/0093 ,  B01J2219/00783 ,  B01J2219/00822 ,  B01J2219/00828 ,  B01J2219/00837 ,  B01J2219/0086 ,  B01L3/502707 ,  B01L2300/0816 ,  B81B2201/058 ,  B81B2203/0338 ,  B81C1/00071 ,  B81C2201/0116 ,  B81C2201/0178 ,  H01L29/16

Abstract: Described herein is a microchannel that is formed beneath and parallel to a surface of a silicon substrate. Silicon migration technology is utilized to form a microchannel that is buried beneath the surface of the silicon substrate. Etching opens at least one end of the microchannel. Oxidization is utilized through the open end of the microchannel to facilitate a controlled diameter of the microchannel.

Abstract translation: 这里描述的是形成在硅衬底的表面下方并平行于其的表面的微通道。 利用硅迁移技术形成埋在硅衬底表面下方的微通道。 蚀刻打开微通道的至少一端。 通过微通道的开口端利用氧化，以促进微通道的受控直径。