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公开(公告)号:US20240314937A1
公开(公告)日:2024-09-19
申请号:US18263621
申请日:2021-04-26
Applicant: LG INNOTEK CO., LTD.
Inventor: Hee Jung LEE , Jin Seok LEE , Yong Han JEON
CPC classification number: H05K3/282 , H05K1/113 , H05K2201/09218 , H05K2203/1377
Abstract: A circuit board according to an embodiment includes an insulating layer including a first region and a second region; a circuit pattern disposed on an upper surface of the first region and an upper surface of the second region of the insulating layer; and a solder resist including a first portion disposed on the upper surface of the first region of the insulating layer and a second portion disposed the upper surface of the second region; wherein a height of the first portion of the solder resist is smaller than a height of the circuit pattern, wherein a height of the second portion of the solder resist is greater than the height of the circuit pattern, wherein at least one of the first region and the second region is divided into a plurality of partial regions, wherein at least one of the first portion and the second portion of the solder resist has a different height in the plurality of partial regions.
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公开(公告)号:US20240306295A1
公开(公告)日:2024-09-12
申请号:US18119268
申请日:2023-03-08
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wen-Long LU
IPC: H05K1/11 , H01L21/768 , H05K1/02 , H05K3/40
CPC classification number: H05K1/115 , H01L21/76871 , H05K1/024 , H05K3/40 , H05K2201/09145 , H05K2201/09218 , H05K2201/095 , H05K2203/0502
Abstract: A circuit structure includes a low-density conductive structure, a high-density conductive structure and a plurality of traces. The high-density conductive structure is disposed over the low-density conductive structure, and defines an opening extending from a top surface of the high-density conductive structure to a bottom surface of the high-density conductive structure. The opening exposes a first pad of the low-density conductive structure and a second pad of the low-density conductive structure. The second pad is spaced apart from the first pad. The traces extend from the top surface of the high-density conductive structure into the opening. The traces include a first trace connecting to the first pad of the low-density conductive structure and a second trace connecting to the second pad of the low-density conductive structure.
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公开(公告)号:US20240268037A1
公开(公告)日:2024-08-08
申请号:US18431231
申请日:2024-02-02
Applicant: Takaroa Corporation, Inc.
Inventor: Ethan M. Devine
CPC classification number: H05K3/4644 , C08L1/02 , H05K1/111 , H05K3/0094 , H05K3/3452 , C08L2203/02 , H05K2201/0137 , H05K2201/09218 , H05K2203/1105 , H05K2203/12 , H05K2203/1333
Abstract: A method for fabricating a printed circuit board comprising preparing a surface of an organic material substrate then depositing conductive traces and at least one conductive pad on the organic material substrate through an additive deposition process. The conductive traces and pads are then heat-treated to create electrically conductive pathways and at least one heat-treated conductive pad. A dielectric material is then deposited through the additive deposition process over a portion of the heat-treated conductive traces to create a dielectric material containing area and a non-dielectric material containing area. The dielectric material containing area is then heat-treated.
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公开(公告)号:US20240098886A1
公开(公告)日:2024-03-21
申请号:US17948893
申请日:2022-09-20
Applicant: DELL PRODUCTS L.P.
Inventor: Sandor Farkas , Bhyrav Mutnury , Timothy M. Lambert
CPC classification number: H05K1/0248 , H01P3/081 , H05K1/0245 , H05K1/05 , H05K2201/09218
Abstract: A printed circuit board includes first and second insulating layers, first and second strip line circuit traces formed on a surface of the first insulating layer, and a patterned dielectric material. The first strip line circuit trace has a first length and carries a first signal. The second strip line circuit trace is adjacent to the first strip line circuit trace, has a second length longer than the first length, and carries a second signal. The patterned dielectric material is provided over a portion of the first length to delay the first signal relative to the second signal. The second insulating layer is affixed to the surface and covers the first and second strip line circuit traces and the patterned dielectric material.
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公开(公告)号:US20180084639A1
公开(公告)日:2018-03-22
申请号:US15554274
申请日:2016-02-09
Applicant: OMRON CORPORATION
Inventor: Wakahiro KAWAI
CPC classification number: H05K1/0284 , H01L2224/20 , H01L2224/24195 , H05K1/185 , H05K2201/0209 , H05K2201/0215 , H05K2201/09118 , H05K2201/09218 , H05K2201/10636 , H05K2203/1469
Abstract: An electronic component (11) is embedded in an end portion of a surface (P1) and an end portion of a surface (P2) adjacent to each other in a three-dimensional base (2). The portion of an electrode (21) exposed from the surface (P1) and an electrode (101) of a packaged IC (41) are connected to each other via a wiring line (201). The portion of the electrode (21) exposed from the surface (P2) and an electrode (25) of an electronic component (15) are connected to each other via a wiring line (202). Accordingly, it is possible to realize a three-dimensional circuit structure requiring no wiring line spanning over or along an end portion thereof.
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公开(公告)号:US20180059828A1
公开(公告)日:2018-03-01
申请号:US15804553
申请日:2017-11-06
Applicant: Wacom Co., Ltd.
Inventor: Yoshiharu Matsumoto
CPC classification number: G06F3/046 , G06F2203/04103 , H05K1/0296 , H05K3/10 , H05K3/28 , H05K2201/09218
Abstract: A terminal, in which terminal conductors are disposed, is preliminarily formed on one surface of a substrate. Electrode conductors including covered lead wires are disposed in a region on the one surface of the substrate that does not overlap the terminal, the electrode conductors being bonded to the substrate by an adhesive material to form a predetermined conductor pattern, whereby a sensor pattern is disposed on the substrate. The lead wires of the electrode conductors are exposed due to the covering being removed at ends of the covered lead wires, the exposed lead wires are disposed while being aligned with and connectable to the corresponding terminal conductors of the terminal. The terminal conductors of the terminal and respective exposed lead wires of the electrode conductors of the sensor pattern are then electrically connected.
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公开(公告)号:US20170347445A1
公开(公告)日:2017-11-30
申请号:US15603554
申请日:2017-05-24
Applicant: Hitachi, Ltd.
Inventor: Rohan BAROT , K. Ramachandra SEKHAR
IPC: H05K1/02
CPC classification number: H05K1/0228 , H05K1/0245 , H05K1/162 , H05K1/165 , H05K2201/09218 , H05K2201/09672
Abstract: The present disclosure relates to a PCB and a method in the PCB for reducing common-mode current. The PCB comprises two differential lines and each of the differential lines is on one or more planes of the PCB. The two differential lines carry a differential mode current and the common mode current. The differential mode current and the common mode current may be at least one of a forward current and a backward current. Further, a predefined configuration is formed using each of the two differential lines to generate impedance at the predefined configuration. Here, the predefined configuration is placed close to each other to generate a dielectric capacitance. The flow of the forward current and the backward current in adjacent tracks of each of the two differential lines in the predefined configuration are in opposite direction.
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公开(公告)号:US20170344151A1
公开(公告)日:2017-11-30
申请号:US15533416
申请日:2015-12-10
Applicant: MITSUBISHI PAPER MILLS LIMITED
Inventor: Takenobu Yoshiki , Kazuhiko Sunada
CPC classification number: G06F3/044 , G06F3/041 , G06F2203/04111 , G06F2203/04112 , H05K1/0274 , H05K1/0289 , H05K2201/0108 , H05K2201/0302 , H05K2201/09218 , H05K2201/09781
Abstract: Provided is an optically transparent conductive material which is suitable as an optically transparent electrode for capacitive touchscreens, the optically transparent conductive material not causing moire even when placed over a liquid crystal display, having a favorably low pattern conspicuousness (non-conspicuousness), and having a high reliability. The optically transparent conductive material has, on an optically transparent support, an optically transparent conductive layer having optically transparent sensor parts electrically connected to terminal parts and optically transparent dummy parts not electrically connected to terminal parts, and in this optically transparent conductive material, the sensor parts and the dummy parts are formed of a metal thin line pattern having a mesh shape, and in the plane of the optically transparent conductive layer, the contour shape of each of the sensor parts extends in a first direction, the dummy parts are arranged alternately with the sensor parts in a second direction perpendicular to the first direction, the sensor parts are arranged at a cycle of L in the second direction, at least part of the metal thin line pattern in the sensor parts has a cycle of 2L/N in the second direction (wherein N is any natural number), and the metal thin line pattern in the dummy parts has a cycle longer than 2L/N or does not have a cycle in the second direction.
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公开(公告)号:US09713252B2
公开(公告)日:2017-07-18
申请号:US15141997
申请日:2016-04-29
Applicant: HE BEI SINOPACK ELECTRONIC TECH CO., LTD.
Inventor: Fei Ding , Linjie Liu , Lei Zhang
CPC classification number: H05K1/0306 , H01L23/13 , H05K1/0213 , H05K1/0243 , H05K1/0298 , H05K1/112 , H05K3/005 , H05K3/188 , H05K3/40 , H05K3/4038 , H05K3/4617 , H05K2201/0723 , H05K2201/09218 , H05K2201/09618 , H05K2201/10303
Abstract: The present invention discloses a ceramic insulator for electronic packaging and a method for fabricating the same, and relates to a technical field of outer shell packaging of electronic devices. Under the circumstance of using neither a chemical coating nor any bonding wire connection circuit, through a design that builds a electroplated circuit into the ceramic insulator, the method accomplishes coating of a nickel alloy protection layer onto a porcelain by an electroplating method, so that not only quality of a coating layer but also requirement of a complete appearance can be ensured. All circuits of the ceramic insulator fabricated by the aforesaid method can conduct with external circuits, such that the electroplating method can be used to accomplish coating of the nickel alloy layer, after accomplishment of all metal coating, metallization parts on an end surface of the porcelain is removed.
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公开(公告)号:US20170025731A1
公开(公告)日:2017-01-26
申请号:US15285625
申请日:2016-10-05
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Noboru KATO , Satoshi ISHINO , Jun SASAKI , Kuniaki YOSUI , Takahiro BABA , Nobuo IKEMOTO
CPC classification number: H01P3/02 , H01P3/003 , H01P3/026 , H01P3/08 , H01P3/082 , H01P3/085 , H01P5/00 , H01P5/028 , H05K1/0218 , H05K1/0221 , H05K1/0237 , H05K1/0242 , H05K1/025 , H05K1/028 , H05K1/0296 , H05K1/14 , H05K1/148 , H05K1/186 , H05K3/361 , H05K2201/0707 , H05K2201/09218
Abstract: A transmission line portion of a flat cable includes first regions and second regions connected alternately. In the first region, the transmission line portion is a flexible tri-plate transmission line including a dielectric element including a signal conductor, a first ground conductor including opening portions, and a second ground conductor which is a solidly filled conductor. In the second region, the transmission line portion is a hard tri-plate transmission line including a wide dielectric element including a meandering conductor, and a first ground conductor and a second ground conductor which are solidly filled conductors. A variation width of the characteristic impedance in the second region is larger than a variation width of the characteristic impedance in the first region.
Abstract translation: 扁平电缆的传输线部分包括交替连接的第一区域和第二区域。 在第一区域中,传输线部分是包括具有信号导体的介质元件,包括开口部分的第一接地导体和作为固体填充导体的第二接地导体的柔性三板传输线。 在第二区域中,传输线部分是包括具有曲折导体的宽电介质元件和固体填充导体的第一接地导体和第二接地导体的硬三板传输线。 第二区域中的特性阻抗的变化幅度大于第一区域中的特性阻抗的变化宽度。
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