公开(公告)号：EP4235796A1

公开(公告)日：2023-08-30

申请号：EP22205699.6

申请日：2022-11-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： MC TAGGART, Sarah A. ,  KRISHNASAMY, Rajendran ,  LIU, Qizhi

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/732

Abstract: A semiconductor structure comprising: a dielectric layer (162); an emitter region (140) comprising: a first emitter portion (141) extending through the dielectric layer (162); and a second emitter portion (142) on the first emitter portion and further extending laterally onto the dielectric layer (162); and an additional dielectric layer (163) on the second emitter portion, wherein the dielectric layer (162), the second emitter portion (142), and the additional dielectric layer (163) are wider than the first emitter portion (141), and wherein at least a section of the second emitter portion (142) is narrower than the dielectric layer (162) and the additional dielectric layer (163). Preferably, the second emitter portion (142) increases in width between the dielectric layer (162) and the additional dielectric layer (163)

公开(公告)号：EP4220732A1

公开(公告)日：2023-08-02

申请号：EP22200707.2

申请日：2022-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ontalus, Viorel ,  Long, Justin C. ,  Baiocco, Robert K.

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/732 ,  H01L29/73

Abstract: A vertical bipolar transistor (BJT) comprising a collector region (12b) in a semiconductor substrate (12), a base region (12a) adjacent to the collector region and an emitter (28) extending above the base region and comprising a remnant of a hardmask (16) surrounding a lower portion of the emitter and a stepped region with a reduced cross-section are at the lower portion and which contacts the base region. The emitter region further comprises dielectric sidewall spacers (34), semiconductor sidewall spacers (24a) and an insulating material (14) under the sidewall spacers and the remnant of the hardmask (16). The method of manufacturing comprises a blanket deposition of the hardmask material (16) at the beginning of the method and opening the emitter window (22) through the hardmask.

公开(公告)号：EP4160695A1

公开(公告)日：2023-04-05

申请号：EP22198237.4

申请日：2022-09-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： YU, Hong ,  HOLT, Judson R. ,  DERRICKSON, Alexander M.

IPC: H01L29/735 ,  H01L21/331 ,  H01L29/165 ,  H01L29/06 ,  H01L27/07 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: Embodiments of the disclosure provide a bipolar transistor structure on a semiconductor fin. The semiconductor fin may be on a substrate and may have a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. The semiconductor fin includes a first portion and a second portion adjacent the first portion along the length of the semiconductor fin. The second portion is coupled to a base contact. A dopant concentration of the first portion is less than a dopant concentration of the second portion. An emitter/collector (E/C) material is adjacent the first portion along the width of the semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.

公开(公告)号：EP4513532A1

公开(公告)日：2025-02-26

申请号：EP24154583.9

申请日：2024-01-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： MACHANI, Kashi Vishwanath ,  KÜCHENMEISTER, Frank

IPC: H01L21/56 ,  G02B6/42

Abstract: Structures for a packaged photonics chip and associated methods. The structure comprises a photonics chip, a packaging substrate, a plurality of electrical connections disposed in a gap between the photonics chip and the packaging substrate, and a fillet comprising an underfill material. The fillet is disposed to overlap with a portion of the photonics chip adjacent to the gap, the fillet has a width dimension and a height dimension transverse to the width dimension, and a ratio of the width dimension to the height dimension is greater than or equal to 1.5.

公开(公告)号：EP4496005A1

公开(公告)日：2025-01-22

申请号：EP24151998.2

申请日：2024-01-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： PAWLAK, Bartlomiej J. ,  HOLT, Judson R.

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/08 ,  H01L29/10

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets; an inner sidewall spacer adjacent each of the plurality of gate structures; and corner spacers under the plurality of stacked semiconductor nanosheets.

公开(公告)号：EP4492685A1

公开(公告)日：2025-01-15

申请号：EP24151286.2

申请日：2024-01-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chinthu, Siva Kumar

IPC: H03K3/356

Abstract: Disclosed structures include a single-stage (100) and a multi-stage voltage level shifter. Each structure includes multiple transistors, which are optionally all symmetric low-voltage transistors, and the structures are configured to avoid operation outside the safe operating area (SOA) of such transistors. The single-stage voltage level shifter (100) and the first stage of the multi-stage voltage level shifter can be essentially identical. In operation, input voltage pulses (IN1, IN1B) (including an input voltage pulse transitioning between a first positive voltage (V1) equal to the voltage rating of the transistors and ground) can be received at source nodes of N-type transistors and, in response, output voltage pulses (OUT1i, OUT1Bi) (including an intermediate output voltage pulse transitioning between V1 and a second positive voltage (V2) that is higher than (e.g., double) V1 and an output voltage pulse (OUT1, OUT1B) that transitions between ground and V2) can be output.

公开(公告)号：EP4481802A1

公开(公告)日：2024-12-25

申请号：EP23198961.7

申请日：2023-09-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Tokranov, Anton ,  Gu, Man ,  Kozarsky, Eric Scott ,  Mulfinger, George ,  Yu, Hong

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/762

Abstract: A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.

公开(公告)号：EP4475360A1

公开(公告)日：2024-12-11

申请号：EP23210786.2

申请日：2023-11-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： POZDER, Scott ,  FISHER, Daniel W. ,  MALINOWSKI, John

IPC: H01S5/0232 ,  H01S5/02326 ,  H01S5/02385 ,  H01S5/024

Abstract: Structures including a photonics chip and a cavity-mounted laser chip, and methods of forming and using such structures. The structure comprises a photonics chip including a substrate and a cavity in the substrate. The structure further comprises a laser chip inside the cavity, and a lead frame comprising a first section attached to a portion of the laser chip and a second section attached to a portion of the photonics chip.

公开(公告)号：EP4468046A1

公开(公告)日：2024-11-27

申请号：EP23209581.0

申请日：2023-11-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： HEDRICK, Brittany ,  MELVILLE, Ian ,  WEBSTER, Michael David ,  COX, Harry ,  LUBGUBAN, Jorge ,  KNICKERBOCKER, Sarah

IPC: G02B6/136 ,  G02B6/42 ,  G02B6/122 ,  G02B6/30 ,  G02B6/12

Abstract: Structures for a photonics chip that include a cavity or groove and methods of forming same. The structure comprises a semiconductor substrate including a first opening, a back-end-of-line stack on the semiconductor substrate, and a dielectric layer on the back-end-of-line stack. The back-end-of-line stack includes a pad, and the dielectric layer includes a second opening that extends to the pad. The structure further comprises an electrical interconnect inside the second opening in the dielectric layer. The electrical interconnect includes a sidewall that is separated in a lateral direction from the dielectric layer by a gap.

公开(公告)号：EP4465362A1

公开(公告)日：2024-11-20

申请号：EP24153816.4

申请日：2024-01-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： YU, Hong ,  PRITCHARD, David C. ,  JAIN, Navneet K. ,  MAZZA, James P. ,  FEUILLETTE, Romain H. A.

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with tunable channels and inner sidewall spacers and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; an inner sidewall spacer adjacent each of the plurality of gate structures; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.