公开(公告)号：DE10103313A1

公开(公告)日：2002-08-22

申请号：DE10103313

申请日：2001-01-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  ROEHR THOMAS

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22

Abstract: An MRAM configuration has selection transistors and MTJ layer sequences lying in parallel with each other in a memory cell matrix. A considerable space saving can thus be achieved and therefore the MRAM configuration is less expensive to manufacture and has a greater packing density. In addition, the MRAM configuration allows a rapid read access with a minimal area requirement.

公开(公告)号：DE10017368A1

公开(公告)日：2001-10-11

申请号：DE10017368

申请日：2000-04-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  ESTERL ROBERT ,  HOENIGSCHMID HEINZ ,  KANDOLF HELMUT

IPC: G11C11/22

Abstract: The integrated memory device operating method uses a pulsed plate concept for accessing a selected memory cell (MC0) of the memory cell matrix during each access cycle, with initial potentials applied to the column line (BLt) and the plate line (PL) of a required memory cell prior to it being accessed by activation of the row line (WL0), for switching the memory cell selection transistor (T0). The potential applied to the plate line is pulsed so that the during the access cycle the memory capacitor of the selected memory cell is charged and discharged.

公开(公告)号：DE10010456A1

公开(公告)日：2001-09-20

申请号：DE10010456

申请日：2000-03-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ ,  LAMMERS STEFAN

IPC: G11C11/22 ,  G11C5/14

Abstract: The reference voltage generation device uses reference cells (R1T,R2T ; R1C,R2C) within the ferroelectric memory provided with a logic "0" and a logic "1", at the ends of the word lines (WLT,WLC) along a reference bit line (BLTREF1, BLTREF2 ; BLCREF1,BLCREF2). The ferroelectric memory may be provided via a MOS technology, with a pulsed plate parallel to the bit line for providing a selective-read memory, with a reference or dummy cell at the end of each word line.

公开(公告)号：DE10005619A1

公开(公告)日：2001-08-30

申请号：DE10005619

申请日：2000-02-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  ESTERL ROBERT ,  KANDOLF HELMUT ,  ROEHR THOMAS

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

Abstract: An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.

公开(公告)号：DE10002374A1

公开(公告)日：2001-08-02

申请号：DE10002374

申请日：2000-01-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  BOEHM THOMAS ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/406

Abstract: The memory arrangement has a memory cell field (7) with a number of memory cells driven via word lines and bit lines and a refresh logic circuit (8) for refreshing the memory contents of the memory cell field. A comparator circuit (9) compares a characteristic parameter of at least one memory cell (10) with a reference value (VREF) and activates the refresh logic as required.

公开(公告)号：DE19926766A1

公开(公告)日：2000-12-21

申请号：DE19926766

申请日：1999-06-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG ,  ROEHR THOMAS ,  SCHINDLER GUENTHER ,  HARTNER WALTER ,  BOEHM THOMAS ,  WENDT HERMANN

IPC: H01L29/78

Abstract: According to the invention, two source/drain regions (121, 122) between which a channel region is arranged are provided for on a semiconductor substrate. On the surface of the channel region a gate dielectric (13) is positioned. Above the gate dielectric (13) a ferroelectric layer (14) and a gate electrode (15) are arranged. The ferroelectric layer (14) overlaps one of the source/drain regions (121). To change the polarization of the ferroelectric layer (14) a voltage can be applied between the gate electrode (15) and the overlapped source/drain region (121).