公开(公告)号：USRE38579E1

公开(公告)日：2004-09-14

申请号：US10032285

申请日：2001-12-20

Applicant: George D. Gregoire

Inventor： George D. Gregoire

IPC: H01R909

CPC classification number: H05K3/005 ,  H05K1/095 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/061 ,  H05K3/107 ,  H05K3/1241 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09863 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/025 ,  H05K2203/041 ,  H05K2203/0746 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A wiring board construction includes at least one microvia disposed in a base substrate and includes a deep imprinted cup shaped recess in the top surface thereof. A conductor material is disposed within the recess, and has a portion disposed at the bottom thereof. A conductor disposed at a bottom surface of the substrate opposite to the conductor material bottom portion helps to complete an electrically conductor path through the substrate to help complete an electrically conductive path through the substrate.

公开(公告)号：US20040052932A1

公开(公告)日：2004-03-18

申请号：US10643919

申请日：2003-08-20

Inventor： Yoshitaro Yazaki ,  Yoshihiko Shiraishi ,  Koji Kondo ,  Toshikazu Harada ,  Tomohiro Yokochi

IPC: B05D005/12

CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T428/24917

Abstract: A heated and pressed printed wiring board is made by filling via holes formed in layers of insulating film of the wiring board with an interlayer conducting material. The insulating film is stacked with conductor patterns, and each conductor pattern closes a via hole. The interlayer conducting material forms a solid conducting material in the via holes after a heating a pressing procedure. The solid conducting material includes two types of conducting materials. The first type of conducting material includes a metal, and the second type of conductive material includes an alloy formed by the metal and conductor metal of the conductor patterns. The conductor patterns are electrically connected reliably without relying on mere mechanical contact.

Abstract translation: 通过用层间导电材料填充形成在布线板的绝缘膜层上的孔，制成加压印刷线路板。 绝缘膜与导体图案堆叠，并且每个导体图案封闭通孔。 夹层导电材料在加压压制程序后在通孔中形成固体导电材料。 固体导电材料包括两种类型的导电材料。 第一类导电材料包括金属，第二类导电材料包括由导体图案的金属和导体金属形成的合金。 导体图形可靠地电连接，而不依赖于机械接触。

公开(公告)号：US20030188888A1

公开(公告)日：2003-10-09

申请号：US09808086

申请日：2001-03-13

Inventor： Hirokazu Yoshioka ,  Norio Yoshida ,  Kenichiro Tanaka

IPC: H05K001/11 ,  H05K003/02

CPC classification number: H05K3/4652 ,  H05K1/116 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/0055 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0969 ,  H05K2201/098 ,  H05K2201/09863 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/0796 ,  H05K2203/095 ,  H05K2203/1383 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165

Abstract: A multilayer printed wiring board is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole provided in the insulating layer as bottomed by the conductor layer exposed, a plated layer provided inside the via hole for electric connection between the conductor layers, the via hole being formed to be of a concave curved surface of a radius in a range of 20 to 100 nullm in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole, whereby the equipotential surfaces occurring upon plating the plated layer are curved along the continuing zone to unify the density of current for rendering the plated layer uniform in the thickness without being thinned at the continuing zone.

Abstract translation: 多层印刷电路板形成有多个导体层，绝缘层整体层叠在一起，绝缘层中设置的非穿透通孔由导体层露出的底部，设置在通孔内部的镀层， 所述导体层之间的电连接，所述通孔形成为在通孔的内周到底面的连续区域的半径在20至100μm的范围内的轴向剖视图中的凹曲面的通孔，由此 在电镀镀层时发生的等电势面沿着连续区域弯曲，以统一电流密度，以使电镀层在厚​​度上均匀，而不会在连续区域变薄。

公开(公告)号：US20030188429A1

公开(公告)日：2003-10-09

申请号：US10435279

申请日：2003-05-08

Applicant: International Business Machines Corporation

Inventor： Takayuki Haze ,  Tsuneo Yabuuchi

IPC: H01K003/22 ,  H05K003/02

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/385 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/086 ,  H05K2203/087 ,  H05K2203/1157 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49165

Abstract: The method for producing a printed wiring board comprising the steps of preparing a conductive substrate, forming an insulating layer on one surface of the said substrate, forming at least one via hole in the insulating layer, thermally curing the insulating layer, and reducing at least one oxidized layer formed on the other conductive surface of the substrate during the curing operation. Alternatively, the thermal cure may be accomplished in an atmosphere (e.g., reducing gas, inactive gas, or mixtures thereof) not conducive to oxide formation on metallized circuit surfaces.

Abstract translation: 一种制造印刷电路板的方法，包括以下步骤：制备导电基板，在所述基板的一个表面上形成绝缘层，在绝缘层中形成至少一个通孔，热固化绝缘层，并至少减少 在固化操作期间在基板的另一导电表面上形成一个氧化层。 或者，热固化可以在不利于金属化电路表面上的氧化物形成的气氛（例如还原气体，惰性气体或其混合物）中完成。

公开(公告)号：US20030166331A1

公开(公告)日：2003-09-04

申请号：US10248688

申请日：2003-02-10

Inventor： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC: H01L021/44

CPC classification number: H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3484 ,  H05K2201/09863 ,  H05K2203/043 ,  H05K2203/0568 ,  H05K2203/0594

Abstract: A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at leastwith an opening that exposes the pre-formed bump. Solder material is deposited into the openings and then a reflow process is conducted fusing the solder material and the pre-formed bump together to form a spherical bump. The pre-formed bump and the solder material may be fabricated using different constituents.

Abstract translation: 提供了一种用于在其上具有多个接合焊盘的晶片上形成凸块的凸块制造工艺。 具有暴露各个接合焊盘的多个开口的图案化焊接掩模层形成在晶片上。 通过底部的横截面积中的开口面积以及通过开口的顶部的开口面积比通过中间部分的横截面积的开口面积小， 部分开幕。 将焊料沉积到开口中，然后进行回流工艺，将焊料材料熔合在一起，以在开口内形成球形凸块。 最后，去除焊接掩模层。 此外，在晶片上形成图案化的焊料掩模层之前，至少具有暴露预形成的凸块的开口，可以在晶片的焊盘上形成预先形成的凸点。 将焊料沉积到开口中，然后进行回流工艺，将焊料材料和预形成的凸块熔合在一起形成球形凸块。 可以使用不同的成分制造预形成的凸块和焊料材料。

公开(公告)号：US20030150644A1

公开(公告)日：2003-08-14

申请号：US10367711

申请日：2003-02-19

Applicant: Ibiden Co., Ltd.

Inventor： Masaru Takada ,  Kiyotaka Tsukada ,  Hiroyuki Kobayashi ,  Hisashi Minoura ,  Yoshikazu Ukai ,  Mitsuhiro Kondo

IPC: H05K003/42

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: In production of a printed wiring board comprising innerlayer conductor circuits 161, 131 arranged among insulating layers 101null103 and blind via-holes 141, 142 formed from an outermost surface of the insulating layer toward the innerlayer conductor circuit, an opening hole 160 is previously formed in a central portion of the innerlayer conductor circuit 161 located at the bottom of the blind via-hole 141, and laser beams are irradiated from the outermost surface of the insulating layer to form the blind via-holes 141, 142. Thereafter, a metal plated film is formed on surfaces of the innerlayer conductor circuits 131, 161 and the blind via-holes 141, 142.

Abstract translation: 在制造印刷布线板时，包括布置在绝缘层101〜103之间的内层导体电路161,131和从绝缘层的最外表面向内层导体电路形成的盲通孔141,142，预先设置有开孔160 形成在位于盲孔通孔141的底部的内层导体电路161的中心部分，并且从绝缘层的最外表面照射激光束以形成盲通孔141,142。此后， 在内层导体电路131,161和盲通孔141,142的表面上形成金属电镀膜。

公开(公告)号：US20030102158A1

公开(公告)日：2003-06-05

申请号：US10281463

申请日：2002-10-25

Inventor： Miguel A. Jimarez ,  Ross W. Keesler ,  Voya R. Markovich ,  Rajinder S. Rai ,  Cheryl L. Tytran-Palomaki

IPC: H05K001/00 ,  H05K001/03

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/3484 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09863 ,  H05K2203/043 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A chip carrier structure and method for forming the same having a receptor pad formed therein. The structure comprises a circuitized substrate having a conductive element on the surface, an External Dielectric Layer mounted on the circuitized substrate with an opening positioned above the conductive element to form a microvia. The walls of the microvia are first treated to enhance copper adhesion and then are electroplated to provide a receptor pad. Finally, a solder paste is deposited within the microvia to create a solder deposit or bump.

公开(公告)号：US20020179335A1

公开(公告)日：2002-12-05

申请号：US10197125

申请日：2002-07-17

Applicant: International Business Machines Corporation

Inventor： Brian Eugene Curcio ,  Peter Alfred Gruber ,  Frederic Maurer ,  Konstantinos I. Papathomas ,  Mark David Poliks

IPC: H01R012/04 ,  H05K003/02

CPC classification number: H05K3/4069 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/4602 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0126 ,  H05K2203/085 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/53191 ,  H01L2924/00

Abstract: High aspect ratio (5:1-30:1) and small (5 nullm-125 nullm) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.

公开(公告)号：US06452117B2

公开(公告)日：2002-09-17

申请号：US09871555

申请日：2001-05-31

Applicant: Brian Eugene Curcio ,  Peter Alfred Gruber ,  Frederic Maurer ,  Konstantinos I. Papathomas ,  Mark David Poliks

Inventor： Brian Eugene Curcio ,  Peter Alfred Gruber ,  Frederic Maurer ,  Konstantinos I. Papathomas ,  Mark David Poliks

IPC: H01R1204

CPC classification number: H05K3/4069 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/4602 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0126 ,  H05K2203/085 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/53191 ,  H01L2924/00

Abstract: High aspect ratio (5:1-30:1) and small (5 &mgr;m-125 &mgr;m) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.

Abstract translation: 提供介电基片中的高纵横比（5：1-30：1）和小（5毫米-125毫米）直径的孔，填充有凝固的导电材料，以及使用压力填充这些孔的方法 和真空。 在某些实施例中，孔用导电材料衬里和/或用导电材料封盖。 本发明还考虑由这种材料形成的芯片载体。

公开(公告)号：US4940181A

公开(公告)日：1990-07-10

申请号：US333670

申请日：1989-04-06

Applicant: Frank J. Juskey, Jr. ,  Barry M. Miles ,  Anthony B. Suppelsa

Inventor： Frank J. Juskey, Jr. ,  Barry M. Miles ,  Anthony B. Suppelsa

IPC: B23K1/20 ,  H05K1/11 ,  H05K3/34 ,  H05K3/46

CPC classification number: B23K1/203 ,  H05K1/111 ,  H05K1/112 ,  H05K3/3436 ,  B23K2201/40 ,  H01L2224/16237 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09745 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/10734 ,  H05K2203/048 ,  H05K3/4644 ,  Y02P70/611 ,  Y02P70/613

Abstract: A pad grid array comprises an array of cavities (12) formed in a circuit carrying substrate (10) that are metallized (18, 20, and 22) to provide electrical conductivity. The metallized cavities are preferably hemispherical in shape and approximately the size of the solder bumps (30) coupled to a solder bumped chip carrier (28) that will be mounted thereon. Flux (26) is applied to each of the metallized cavities before positioning the solder bumped chip (28) carrier over the pad grid array. Proper mounting can be detected by tactile sensing in either human or robotic assemblers when the solder bumps "drop" into the metallized cavities.

Abstract translation: 垫栅格阵列包括形成在电路承载衬底（10）中的金属化（18,20和22）以提供导电性的空腔阵列（12）。 金属化腔体的形状优选为半球形，并且大致与焊接凸块（30）的尺寸相连接，其将被安装在其上的焊料凸起的芯片载体（28）上。 在将焊料凸起的芯片（28）载体定位在焊盘格栅阵列上之前，将焊剂（26）施加到每个金属化空腔。 当焊料凸起“掉入”到金属化空腔中时，可以通过人体或机器人组装器中的触觉感测来检测正确的安装。