公开(公告)号：EP4462679A1

公开(公告)日：2024-11-13

申请号：EP23208142.2

申请日：2023-11-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chinthu, Siva Kumar ,  Ara, Venu Gopal Reddy ,  Dwivedi, Devesh

IPC: H03K5/133 ,  H03K19/0185 ,  H03K19/20

Abstract: Embodiments of the disclosure provide a customizable logic cells and related methods to form the same. A structure (100) of the disclosure includes a first pair of complementary transistors (112) connected in series between a first voltage node (V1) and a second voltage node (V2). Each transistor of the first pair includes a gate coupled to a first input node (N1). A second pair of complementary transistors (114) is connected in series between the first voltage node (V1) and the second voltage node (V2) in an opposite orientation from the first pair of complementary transistors. Each transistor of the second pair includes a gate coupled to a second input node (N2). An output line (Vout) is coupled to a first electrical connection between the first pair complementary transistors and a second electrical connection between the second pair of complementary transistors.

公开(公告)号：EP4443518A1

公开(公告)日：2024-10-09

申请号：EP23198431.1

申请日：2023-09-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： HOLT, Judson R. ,  PEKARIK, John J. ,  NATH, Anindya ,  MITRA, Souvick

IPC: H01L29/737 ,  H01L21/331 ,  H01L29/06 ,  H01L29/87 ,  H01L29/78

CPC classification number: H01L29/7371 ,  H01L29/66242 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/87 ,  H01L29/78 ,  H01L29/66628 ,  H01L29/1054 ,  H01L29/32

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to low capacitance, low resistance devices and methods of manufacture. The structure includes: a semiconductor substrate; a device having an active region; and a porous semiconductor material within the semiconductor substrate and surrounding the active region of the device.

公开(公告)号：EP4439139A1

公开(公告)日：2024-10-02

申请号：EP23198430.3

申请日：2023-09-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： DASGUPTA, Arpan ,  BIAN, Yusheng ,  SAFRAN, John M. ,  ROBSON, Norman

IPC: G02B6/122 ,  G02B6/30

CPC classification number: G02B6/30 ,  G02B6/1228 ,  G02B6/124

Abstract: Structures including multiple photonics chips and methods of fabricating a structure including multiple photonics chips. The structure comprises a first chip including a first edge and a first plurality of optical couplers disposed at the first edge, and a second chip including a second edge adjacent to the first edge of the first chip and a second plurality of optical couplers. The second plurality of optical couplers are disposed at the second edge adjacent to the first plurality of optical couplers.

公开(公告)号：EP4400883A3

公开(公告)日：2024-10-02

申请号：EP23205378.5

申请日：2023-10-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： BIAN, Yusheng

IPC: G02B6/125 ,  G02B6/12

CPC classification number: G02B2006/1214720130101 ,  G02B6/125

Abstract: Structures for a directional coupler and methods of forming a structure for a directional coupler. The structure comprises a first waveguide core including a first plurality of segments, and a second waveguide core including a second plurality of segments disposed adjacent to the first plurality of segments in a coupling region. The structure further comprises a first cladding layer comprising a first material that has a first refractive index, and a second cladding layer comprising a second material that has a second refractive index different from the first refractive index. The first cladding layer adjoins a first sidewall of each of the first plurality of segments and a first sidewall of each of the second plurality of segments, and the second cladding layer adjoins a second sidewall of each of the first plurality of segments and a second sidewall of each of the second plurality of segments.

公开(公告)号：EP4425228A1

公开(公告)日：2024-09-04

申请号：EP23192904.3

申请日：2023-08-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： BIAN, Yusheng ,  DEZFULIAN, Kevin ,  GIEWONT, Kenneth ,  NUMMY, Karen

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/136 ,  G02B6/125

CPC classification number: G02B6/1228 ,  G02B2006/1214720130101 ,  G02B2006/1203520130101 ,  G02B6/136 ,  G02B6/12002 ,  G02B6/125

Abstract: Structures for a waveguide escalator and methods of forming such structures. A structure comprises a first waveguide core (12), and a back-end-of-line stack (24) including a first dielectric layer (26), a second dielectric layer (28) on the first dielectric layer (26), an opening (32) in the second dielectric layer (28), a second waveguide core (42) including a section that overlaps with a section of the first waveguide core (12), and a plurality of third waveguide cores (34,36,38) disposed between the section of the first waveguide core (12) and the section of the second waveguide core (42). The plurality of third waveguide cores (34,36,38) are positioned inside the opening in the second dielectric layer, the first dielectric layer (26) comprises a first material with a first refractive index, and the second dielectric layer (28) comprises a second material with a second refractive index different from the first refractive index.

公开(公告)号：EP4421878A1

公开(公告)日：2024-08-28

申请号：EP23205667.1

申请日：2023-10-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： HEBERT, Francois ,  COOPER, James A. ,  MADDI, Hema Lata Rao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/51 ,  H01L21/336 ,  H01L29/10

CPC classification number: H01L29/0623 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7813 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/0878

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate comprising a wide bandgap semiconductor material, a gate electrode, a first gate dielectric layer disposed on the semiconductor substrate, and a second gate dielectric layer disposed between the first gate dielectric layer and the gate electrode.

公开(公告)号：EP4421874A1

公开(公告)日：2024-08-28

申请号：EP24152507.0

申请日：2024-01-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： PANDEY, Shesh Mani ,  KARALKAR, Sagar Premnath ,  KRISHNASAMY, Rajendran ,  TAN, Chung Foong

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/329 ,  H01L29/87

CPC classification number: H01L29/87 ,  H01L29/66121 ,  H01L29/0649 ,  H01L29/1604

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high performance silicon controlled rectifier (SCR) devices and methods of manufacture. The structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; and a porous semiconductor region extending in the first well and the second well.

公开(公告)号：EP4354511A3

公开(公告)日：2024-08-07

申请号：EP23195277.1

申请日：2023-09-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： ZIERAK, Michael J. ,  BENTLEY, Steven J. ,  SHARMA, Santosh ,  LEVY, Mark D. ,  KANTAROVSKY, Johnatan A.

IPC: H01L29/41 ,  H01L29/778 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/778 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/402 ,  H01L29/1066

Abstract: A structure includes at least one gate structure (20, 22, 38) over semiconductor material (16), the at least one gate structure comprising an active layer (20), a gate metal (38) extending from the active layer and a sidewall spacer (34) on sidewalls of the gate metal; and a field plate (26) aligned with the at least one gate structure and isolated from the gate metal by the sidewall spacer.

公开(公告)号：EP4407671A1

公开(公告)日：2024-07-31

申请号：EP23194266.5

申请日：2023-08-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： McKay, Thomas G. ,  Katzman, Gail B.

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H03K17/14 ,  H03K17/16 ,  H03K17/10 ,  H04B1/04

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/78648 ,  H04B1/0458 ,  H03K17/102 ,  H03K17/302 ,  H03K2217/001820130101

Abstract: A disclosed structure (e.g., a switch circuit) includes multiple transistors (e.g., on triple wells) connected in series between a first and second nodes. Each transistor can include a primary gate (e.g., a front gate) for controlling the ON/OFF state of the transistor and a secondary gate (e.g., a back gate) for adjusting the VT of the transistor. The switch circuit further includes multiple capacitors (e.g., APMOM capacitors on triple wells), each connected to the second node and to the secondary gate of a corresponding one of the transistors. In advanced semiconductor-on-insulator processing technology platforms, each secondary gate includes a well region within a semiconductor substrate and a corresponding section of an insulator layer, which is on the semiconductor substrate and adjacent to an active device region for the transistor. The capacitors are preselected during design and different capacitances for limiting parasitic secondary gate-to-substrate coupling. Also disclosed are associated methods.

公开(公告)号：EP4376094A3

公开(公告)日：2024-07-31

申请号：EP23196323.2

申请日：2023-09-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Borisov, Kiril Biserov ,  Darwish, Mohammed Ahmed Fouad Ibrahim ,  Weisbuch, Francois C. ,  Elshafie, Shady Ahmed Abdelwahed Ahmed ,  Pritchard, David Charles ,  Ramadout, Benoit Francois Claude

IPC: H01L29/78 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L29/0692 ,  H01L29/78

Abstract: Embodiments of the disclosure provide a gate structure over a corner segment of a semiconductor region. A structure according to the disclosure includes a semiconductor region within a substrate. The semiconductor region includes a first edge, a second edge oriented perpendicularly to the first edge, and a first corner segment connecting the first edge to the second edge. A first gate structure extends over the first edge, and entirely covers the first edge and the first corner segment of the semiconductor region.