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    121.
    发明专利
    未知

    公开(公告)号：DE69331052D1

    公开(公告)日：2001-12-06

    申请号：DE69331052

    申请日：1993-07-01

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： ZAMBRANO RAFFAELE ,  LEONARDI SALVATORE ,  CACCIOLA GIOVANNA

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L21/329 ,  H01L21/336 ,  H01L21/761

    Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region (3,7) of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first lightly doped ring (4) of the first conductivity type obtained in a first lightly doped epitaxial layer (2) of a second conductivity type and surrounding said diffused region (3,7), and a second lightly doped ring (8) of the first conductivity type, superimposed on and merged with said first ring (4), obtained in a second lightly doped epitaxial layer (6) of the second conductivity type grown over the first epitaxial layer (2).

    122.
    发明专利
    未知

    公开(公告)号：DE69521210T2

    公开(公告)日：2001-11-22

    申请号：DE69521210

    申请日：1995-12-29

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： AIELLO NATALE ,  GRAZIANO VITO

    IPC: H01L27/02 ,  H01L27/082 ,  H01L29/00

    Abstract: The present invention relates to an electronic device integrated monolithically on a semiconductor material comprising a substrate (1) having a first conductivity type in which are formed a first (2) and second diffusion regions (3) of a second conductivity type with said substrate (1) and said first (2) and second (3) diffusion regions including respectively a base region, a collector region and an emitter region of a transistor (Tp1) and characterized in that in the second diffusion region (3) is formed a third diffusion region (8) having conductivity of the first type to provide in said second diffusion region (3) a resistive path (R) placed in series with the emitter region of the transistor (Tp1) while backfeeding it negatively and taking it to saturation with a resulting reduction of its current gain and limitation of the maximum current due thereto.

    124.
    发明专利
    未知

    公开(公告)号：DE69329999T2

    公开(公告)日：2001-09-13

    申请号：DE69329999

    申请日：1993-12-29

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： RONSISVALLE CESARE

    IPC: H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L21/76 ,  H01L21/82

    Abstract: A process for the manufacturing of integrated ciruits comprises the steps of: forming an oxide layer (5,6) on at least one surface of two respective semiconductor material wafers (1,2); obtaining a single semiconductor material wafer with a first layer (3,9) and a second layer (2) of semiconductor material and a buried oxide layer (8) interposed therebetween starting from said two semiconductor material wafers (1,2) by direct bonding of the oxide layers (5,6) previously grown; submitting the single wafer to a controlled reduction of the thickness of the first layer (3,9) of semiconductor material; lapping a top surface of the first layer (3,9) of semiconductor material; selectively introducing dopant impurities into selected regions (12,13,14) of the first layer (3,9) of semiconductor material to form the desired integrated components; forming trenches (18) laterally delimiting respective portions of the first layer (3,9) of semiconductor material wherein integrated components are present which are to be electrically isolated from other integrated components; filling the trenches (18) with an insulating material (20).

    125.
    发明专利
    未知

    公开(公告)号：DE69614248D1

    公开(公告)日：2001-09-06

    申请号：DE69614248

    申请日：1996-05-31

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PISATI VALERIO ,  ALINI ROBERTO ,  COSENTINO GAETANO ,  VAI GIANFRANCO

    IPC: H03F3/45 ,  H03F3/72 ,  H03H1/00

    Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2). In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).

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