公开(公告)号：DE10101951A1

公开(公告)日：2002-08-01

申请号：DE10101951

申请日：2001-01-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHIENLE MEINRAD ,  THEWES ROLAND

IPC: H01L27/07 ,  H01L27/08 ,  H03K19/096

Abstract: The substrate contains a P-doped trough region, in which is formed an N-doped source region and an N-doped drain region. Between the source and drain region is located an insulation layer and carries a gate region. A drain electrode is coupled to the drain region and a source electrode to the source region. To the trough region is linked a trough electrode for energizing the PN-junction between the trough and drain regions as a diode. The doping polarities may be inverted.

公开(公告)号：DE59609221D1

公开(公告)日：2002-06-27

申请号：DE59609221

申请日：1996-03-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VON BASSE PAUL-WERNER ,  BOLLU DR ,  THEWES ROLAND ,  SCHMITT-LANDSIEDEL DR

IPC: G11C8/04 ,  G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G11C29/00 ,  G11C29/42

Abstract: The memory has a memory matrix (SM), with the memory cells (11,...ZS) coupled to row and column lines (ZL,SL). They are respectively associated with row and column selection devices (ZPTR ; SPTR,SCH), which are each indexed by a given step in response to each clock signal (CLK). The selection devices are formed so that when a new row is selected, only a limited number of columns can be selected and/or when a new column is selected only a limited number of rows can be selected. Pref. each selection device uses a number of shift registers connected in a ring.

公开(公告)号：AT217987T

公开(公告)日：2002-06-15

申请号：AT96104260

申请日：1996-03-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VON BASSE PAUL-WERNER ,  BOLLU MICHAEL DR ,  THEWES ROLAND ,  SCHMITT-LANDSIEDEL DORIS DR

IPC: G11C8/04 ,  G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G11C29/00 ,  G11C29/42

Abstract: The memory has a memory matrix (SM), with the memory cells (11,...ZS) coupled to row and column lines (ZL,SL). They are respectively associated with row and column selection devices (ZPTR ; SPTR,SCH), which are each indexed by a given step in response to each clock signal (CLK). The selection devices are formed so that when a new row is selected, only a limited number of columns can be selected and/or when a new column is selected only a limited number of rows can be selected. Pref. each selection device uses a number of shift registers connected in a ring.

公开(公告)号：DE10040422A1

公开(公告)日：2002-03-07

申请号：DE10040422

申请日：2000-08-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAUERBREY JENS ,  WITTIG MARTIN ,  THEWES ROLAND

IPC: H03H19/00 ,  H03K5/151 ,  H03K5/24 ,  H03F3/38 ,  H03F3/45 ,  H03F3/72

Abstract: A circuit arrangement in switched op.amp. technique has at least one switched op.amp and at least one sampling capacitor connected to the output of the op.amp. and a clock-pulse/signal generating device for generating at least two non-overlapping switched clock-pulses/signals (46,47).A device is provided for varying the switched clock phases (50,51) in which all switched clock pulses/signals are in the OFF-phase.

公开(公告)号：DE10027914A1

公开(公告)日：2001-12-13

申请号：DE10027914

申请日：2000-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DAHL CLAUS ,  ROBL WERNER ,  ROEHNER MICHAEL ,  GSCHWANDTNER ALEXANDER ,  JURK REINHARD ,  THEWES ROLAND

IPC: H01L23/00 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/336

Abstract: The invention relates to a component with a transistor and method for production thereof. According to the invention, the cut-off voltage drift of PMOS transistors may be reduced, whereby a getter layer (14) with a thickness of at least 40 nm is provided in conductor tracks above the PMOS transistor.

公开(公告)号：DE10015818A1

公开(公告)日：2001-10-18

申请号：DE10015818

申请日：2000-03-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREY ALEXANDER ,  THEWES ROLAND

IPC: G01N27/30 ,  C12M1/00 ,  C12M1/34 ,  C12N15/09 ,  C12Q1/68 ,  G01N27/22 ,  G01N27/327 ,  G01N27/403 ,  G01N27/416 ,  G01N27/49 ,  G01N33/487 ,  G01N33/483

Abstract: The invention relates to a first electrode that is provided with a holding area for holding probe molecules which can bind macromolecular biopolymers. The first electrode and/or a second electrode is/are divided into a plurality of electrode segments that are electrically insulated from one another. The randomly selected electrode segments, independently from one another, can be electrically coupled in such a way that an effective electrode surface can be adjusted in the size thereof according to the selected electrode segments.

公开(公告)号：DE59606519D1

公开(公告)日：2001-04-05

申请号：DE59606519

申请日：1996-06-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THEWES ROLAND ,  PRANGE STEFAN ,  WOHLRAB ERDMUTE ,  WEBER WERNER

IPC: G06F7/53 ,  G06F7/501 ,  G06F7/52 ,  G06F7/523 ,  H03K5/24 ,  H03K19/20

Abstract: PCT No. PCT/DE96/00972 Sec. 371 Date Dec. 4, 1997 Sec. 102(e) Date Dec. 4, 1997 PCT Filed Jun. 3, 1996 PCT Pub. No. WO96/42050 PCT Pub. Date Dec. 27, 1996The circuit arrangement compares a quantity supplied by a first neuron MOS field effect transistor (M1) to a reference quantity that is made available by a reference source (R). A current mirror (SP) is provided therefor, this enabling a comparison of a second current (I2) supplied by a reference transistor (R) to a first current (I1) supplied by the first neuron MOS field effect transistor (M1). The evaluator circuit is activated or, respectively, decoupled by a first switch unit (S1) and a second switch unit (S2). What is thereby achieved is that no current flows in the evaluator circuit in the quiescent condition. The comparison result is applied to an inverter unit (IS). Since the inverter unit (IS) is decoupled from the evaluator circuit by the first switch unit (S1), an undefined level is never adjacent at the output (AIS) of the inverter unit (IS). This can be advantageously utilized in the further data processing in following stages.

公开(公告)号：DE19947118C1

公开(公告)日：2001-03-15

申请号：DE19947118

申请日：1999-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEBER WERNER ,  THEWES ROLAND

IPC: G01R31/28 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  G11C29/04 ,  G11C29/56 ,  G11C7/00

Abstract: The invention relates to a method and a circuit (20) for evaluating the information content of a memory cell (10), preferably an MRAM memory cell, or a memory cell field. The aim of the invention is to carry out a precise, reliable evaluation of the memory cell (10). A first value representing the current passing through the memory cell (10) or a voltage value that is correlated with said current value is measured, guided through a first circuit branch (23), which has a switch (24) and a capacitor (25), and temporarily stored. The memory cell (10) is then subjected to a programming operation. A second current value or voltage value is subsequently measured in the same memory cell (10), guided through a second circuit branch (26), which has a switch (27) and a capacitor (28), and temporarily stored there. The two measured values are compared with each other in an evaluator (21).

公开(公告)号：DE59702679D1

公开(公告)日：2001-01-04

申请号：DE59702679

申请日：1997-07-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THEWES ROLAND ,  WEBER WERNER ,  LUCK ANDREAS ,  WOHLRAB ERDMUTE ,  SCHMITT-LANDSIEDEL DORIS

IPC: G06G7/60 ,  H03F1/22 ,  H03F3/16 ,  H03G1/00

Abstract: Amplifier circuits having at least one neuron MOS transistor in which a coupling gate is connected to an amplifier output and at least one further coupling gate is connected with a respective amplifier input are provided. The amplifier circuit exhibits a linear transmission behavior even in large-signal operation and can be constructed using relatively few components. Furthermore, the gain is easy to set.