公开(公告)号：DE69518653D1

公开(公告)日：2000-10-05

申请号：DE69518653

申请日：1995-12-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： GRIMALDI ANTONIO ,  SCHILLACI ANTONINO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/336 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

公开(公告)号：DE69517948D1

公开(公告)日：2000-08-17

申请号：DE69517948

申请日：1995-02-28

Applicant: CONS RIC MICROELETTRONICA

Inventor： AIELLO NATALE

IPC: H01L27/06 ,  H01L21/8222 ,  H01L27/02 ,  H03K19/003

Abstract: A circuit (30) for biasing epitaxial wells of a semiconductor integrated circuit comprises a first transistor (T1) and a second transistor (T2) driven in phase opposition to the first; when the supply voltage is positive, the first transistor (T1), being connected between the power supply and the epitaxial well, is conducting whereas the second transistor (T2) is cut off. When, on the contrary, the supply voltage is negative, the second transistor (T2), being connected between the epitaxial well and the ground reference GND, goes into saturation, thereby holding the epitaxial well biased to ground since, at that time, it is the highest potential present on the device. In this way, it becomes possible to always ensure reverse biasing of the parasitic diodes which form at the junctions between the epitaxial wells and the adjacent regions thereto.

公开(公告)号：DE69328251T2

公开(公告)日：2000-08-10

申请号：DE69328251

申请日：1993-11-30

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： MANCUSO MASSIMO ,  POLUZZI RINALDO ,  RIZZOTTO GIANGUIDO

IPC: G06T5/00

公开(公告)号：DE69609053D1

公开(公告)日：2000-08-03

申请号：DE69609053

申请日：1996-05-14

Applicant: CONS RIC MICROELETTRONICA

Inventor： SCACCIANOCE SALVATORE ,  SUERI STEFANO

IPC: H01L21/8224 ,  H01L27/082 ,  H01L29/00

Abstract: An integrated semiconductor structure (500) comprises two homologous P-type regions (120 and 130) formed within an N-type epitaxial layer (110). A P-type region (510) formed in the portion of the epitaxial layer (110) disposed between the two P-type regions (120 and 130) includes within it an N-type region (520); this N region (520) is electrically connected to the P region (130) by means of a surface metal contact (530). The structure reduces the injection of current between the P region 120 and the P region 130, at the same time preventing any vertical parasitic transistors from being switched on.

公开(公告)号：DE69420565T2

公开(公告)日：2000-03-30

申请号：DE69420565

申请日：1994-10-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： CACCIOLA GIOVANNA ,  LEONARDI SALVATORE ,  MONTALBANO GIANPIERO

IPC: H01L21/8234 ,  H01L27/06 ,  H01L27/092

Abstract: The invention relates to a control circuit for semiconductor devices which is formed on a substrate (1) doped by a first dopant type, the integrated circuit comprising a first epitaxial layer (2) grown on the substrate (1) and doped by the first dopant type, and an isolation well (3) doped by a second dopant type, the control circuit comprising at least a first control transistor (M1) formed in a first well (8) doped by the second dopant type and formed in the insulation well (3). Thus, the control circuit comprises at least one N-channel MOS transistor accommodated within a well in direct contact with the isolation well to eliminate a buried layer that, in prior art arrangements, involved the presence of an undesired parasitic component.

公开(公告)号：DE69421083T2

公开(公告)日：2000-03-16

申请号：DE69421083

申请日：1994-11-17

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： COLLETTI PAOLO ,  BONTEMPO GREGORIO ,  PULVIRENTI FRANCESCO ,  GARIBOLDI ROBERTO

IPC: H01L27/04 ,  G05F1/573 ,  H01L21/822 ,  H01L29/78 ,  H02H7/00 ,  H03K17/08 ,  H02H9/02

Abstract: The purpose of the present invention is to supply a method and a circuit simple and accurate enough to protect at least one transistor against exceeding a complex limit implying processing of multiple electrical quantities associated with said transistor. Since in many practical cases said complex limit corresponds to the product of at least two quantities, typically a current and a voltage, the circuit in accordance with the present invention generates electrical signals basically proportional to said quantities, multiplies them, compares the product with a reference signal corresponding to the limit placed on the transistor and acts on the transistor in such a way that said limit is not exceeded. Advantageously the multiplication of currents can be provided simply by means of connection in series of bipolar transistor junctions at which said currents are supplied to the respective emitters. In this case it is additionally advantageous to generate the reference signal by means of connection in series of the bipolar transistor junctions in such a manner as to have an analogous behaviour of the multiplier and the generator.

公开(公告)号：DE69326543D1

公开(公告)日：1999-10-28

申请号：DE69326543

申请日：1993-04-28

Applicant: CONS RIC MICROELETTRONICA

Inventor： PALARA SERGIO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/732 ,  H01L29/78 ,  H01L27/08

Abstract: A structure of an electronic device having a predetermined unidirectional conduction threshold, being formed on a chip of an N-semiconductor material, comprises a plurality of isolated N-regions (16a-c), each bounded laterally by an isolating region (15a-c) and at the bottom by two buried P- and N-regions which form in combination a junction with a predetermined reverse conduction threshold, and means (15a,18,17b,15b,17c) of connecting the junctions of the various isolated regions serially together in the same conduction sense; the buried N-region of the first junction (Z1) in the series is connected to a common electrode (C), which also is one terminal of the device, over an internal path (R) of the N-material of the chip, and the buried P-region of the last junction (Zn) in the series contains an additional buried N-region (14d) which is connected electrically to a second terminal (18a) of the device.

公开(公告)号：DE69229927D1

公开(公告)日：1999-10-14

申请号：DE69229927

申请日：1992-03-17

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO FRISINA FERR ,  FERLA GIUSEPPE

IPC: H01L21/22 ,  H01L21/322 ,  H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/07 ,  H01L27/082 ,  H01L29/732 ,  H01L29/861

Abstract: The structure consists of a single chip (1) of semiconductor material, which comprises an area (32) having a high lifetime of the minority carriers, which constitutes a bipolar power device with high current density, and at least one area (20, 21; 20', 21') with a reduced lifetime of the minority carriers, which constitutes a fast diode.

公开(公告)号：DE69326237D1

公开(公告)日：1999-10-07

申请号：DE69326237

申请日：1993-06-15

Applicant: CONS RIC MICROELETTRONICA

Inventor： APARO SEBASTIANO ,  PATTI ALFONSO ,  VITANZA ALDO

IPC: H01L27/06 ,  H01L27/07

公开(公告)号：DE69325645D1

公开(公告)日：1999-08-19

申请号：DE69325645

申请日：1993-04-21

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L29/78 ,  H01L27/02 ,  H01L27/04

Abstract: An integrated structure protection device suitable for protecting a power MOS device from electro static discharges comprises a junction diode (9) comprising a first electrode made of a highly doped region (12) of a first conductivity type surrounded by a body region (11) of a second conductivity type and representing a second electrode of the junction diode (9), which in turn is surrounded by a highly doped deep body region (10) of said second conductivity type. The highly doped region (12) is connected to a polysilicon gate layer (7) representing the gate of the power MOS device, while the deep body region (10) is connected to a source region (6) of the power MOS.