公开(公告)号：KR1020050066963A

公开(公告)日：2005-06-30

申请号：KR1020040061205

申请日：2004-08-03

Applicant: 한국전자통신연구원

Inventor： 권성구 ,  김종대 ,  노태문 ,  유병곤

IPC: H01L21/336

Abstract: 본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 벌크 실리콘 기판을 사용하는 FIN-FET 또는 Tri-gate 소자 제조시 FIN 채널의 정확한 높이 제어와 높이 균일도 특성을 확보할 수 있을 뿐만 아니라 공정 수행이 용이하고, 단순하여 양산화가 용이한 반도체 소자의 제조 방법에 관한 것이다.
본 발명의 반도체 소자의 제조 방법은, 반도체 소자의 제조 방법에 있어서, (a) 실리콘 기판 상에 실리콘 산화막의 단층막으로 이루어진 소자 절연막을 형성하는 단계; (b) 상기 소자 절연막 상에 감광막 패턴을 형성시킨 후, 상기 감광막 패턴을 식각 마스크로 이용하여 활성 영역을 형성하기 위해 상기 소자 절연막을 식각하고, 상기 감광막 패턴을 제거한 다음 세정공정을 실시하는 단계; (c) 상기 형성된 활성 영역에 채널용 에피막을 상기 소자 절연막의 최상부위로 올라오도록 과잉성장하는 단계; (d) 상기 과잉성장된 채널용 에피막을 상기 소자 절연막 상부까지 식각하는 단계; (e) 상기 소자 절연막을 일정한 두께만큼 식각 및 평탄화 하는 단계; 및 (f) 상기 결과물의 전체 상부면에 순차적으로 게이트 절연막 및 게이트 전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.

公开(公告)号：KR1020050066933A

公开(公告)日：2005-06-30

申请号：KR1020040015071

申请日：2004-03-05

Applicant: 한국전자통신연구원

Inventor： 권성구 ,  노태문 ,  유병곤 ,  김종대

IPC: H01L21/027

CPC classification number: H01L21/0337 ,  G03F7/40 ,  H01L21/0338 ,  H01L21/31144

Abstract: 본 발명은 반도체 소자의 패턴 형성방법에 관한 것으로, (a) 식각하고자 하는 대상층 상부에 제 1 식각 배리어층, 등방성 트리밍층 및 감광막을 형성하는 단계와, (b) 감광막을 패터닝하는 단계와, (c) 패터닝된 감광막을 마스크로 등방성 트리밍층을 비등방성 식각하고, 등방성 식각으로 소정의 선폭이 얻어질 때까지 식각하는 단계와, (d) 잔류한 감광막을 제거하고 패터닝된 상기 등방성 트리밍층을 식각 마스크로 제 1 식각 배리어층 및 대상층을 차례로 패터닝하는 반도체 소자의 패턴 형성방법을 제공한다.

公开(公告)号：KR1020050060170A

公开(公告)日：2005-06-22

申请号：KR1020030091708

申请日：2003-12-16

Applicant: 한국전자통신연구원

Inventor： 권성구 ,  노태문 ,  유병곤 ,  이대우 ,  김종대

IPC: H01L21/20

Abstract: 본 발명은 초박형 SOI 웨이퍼 제조 방법에 관해 개시한다. 내부에는 수소 주입층 및 매몰 산화층이 형성되고, 표면에는 산화막이 형성된 콘트롤 웨이퍼를 준비한다. 상기 콘트롤 웨이퍼의 산화막 표면에 핸들 웨이퍼를 접합한 후 스마트 컷 방법으로 상기 수소 주입층 하부의 콘트롤 웨이퍼를 제거한다. 상기 매몰 산화층 상부의 실리콘 및 상기 매몰 산화층을 제거한 후 노출되는 실리콘을 소정 두께 연마한다. 본 발명의 SOI 웨이퍼는 웨이퍼 수준에서 높은 두께 균일도와 우수한 막질을 갖는 실리콘 활성층을 포함하며, 저비용으로 제조가 가능하다.

公开(公告)号：KR100449070B1

公开(公告)日：2004-09-18

申请号：KR1020010073393

申请日：2001-11-23

Applicant: 한국전자통신연구원

Inventor： 양일석 ,  노태문 ,  김종대 ,  유병곤

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: The present invention relates to a ferroelectric memory cell array formed of a single transistor, and method of storing data using the same. The ferroelectric memory cell array includes a plurality of word lines connected to gates of the memory cells located at respective rows, a plurality of bit lines connected to drains of the memory cells located at respective columns, a common source line commonly connecting sources of the memory cells, and a plurality of well lines each connected to wells in which the memory cells are each formed, wherein a bias voltage of an unit pulse shape is applied to a gate of a selected memory cell and a bias voltage of a pulse shape is applied to a well line. Therefore, the present invention allows a random access without a disturbance since data can be written by means of the polarity characteristic of the ferroelectric.

Abstract translation: 本发明涉及由单个晶体管形成的铁电存储器单元阵列，以及使用该晶体管存储数据的方法。 铁电存储器单元阵列包括连接到位于各行的存储器单元的栅极的多个字线，连接到位于各列的存储器单元的漏极的多个位线，共同连接存储器的源极的公共源极线 单元和多个阱线，每个阱线连接到其中形成有存储器单元的阱，其中，将单位脉冲形状的偏置电压施加到所选择的存储器单元的栅极，并且施加脉冲形状的偏置电压 到井线。 因此，本发明允许无干扰地进行随机存取，因为数据可以通过铁电体的极性特性来写入。

公开(公告)号：KR1020040036410A

公开(公告)日：2004-04-30

申请号：KR1020020065430

申请日：2002-10-25

Applicant: 한국전자통신연구원

Inventor： 유병곤 ,  조성목 ,  유종선 ,  류상욱 ,  유인규 ,  윤성민 ,  김귀동

IPC: H01L31/09 ,  G01J1/02 ,  H01L27/14

Abstract: PURPOSE: An infrared detecting pixel is provided to facilitate fabrication of the structure of a detection part and maximize an effective detecting area by separating the detection part from a substrate having a read-out integrated circuit by a gap and by electrically connecting electrodes of the detection part and the read-out integrated circuit by a pillar. CONSTITUTION: A semiconductor substrate(100) includes the read-out integrated circuit. The detection part detects infrared rays, located over the semiconductor substrate and spatially separated from the substrate. A plurality of support units have a dual cylinder structure made of outer insulation pillars(104a,104b) and inner conductive bridges(106a,106b), connecting the semiconductor substrate with the detection part. A signal detected by the detection part is delivered to the read-out integrated circuit of the semiconductor substrate through the conductive bridge.

Abstract translation: 目的：提供一种红外线检测像素，以便于制造检测部件的结构，并通过将检测部分与具有读出集成电路的基板间隔开来并通过电连接检测电极而使检测部分分离，从而使检测部分最大化 部分和读出的集成电路由一个支柱。 构成：半导体衬底（100）包括读出的集成电路。 检测部分检测位于半导体衬底上并与衬底空间分离的红外线。 多个支撑单元具有由外绝缘柱（104a，104b）和内导电桥（106a，106b）制成的双圆筒结构，其将半导体衬底与检测部分连接。 由检测部检测的信号通过导电桥传送到半导体基板的读出集成电路。

公开(公告)号：KR1020040032376A

公开(公告)日：2004-04-17

申请号：KR1020020061487

申请日：2002-10-09

Applicant: 한국전자통신연구원

Inventor： 양일석 ,  김종대 ,  노태문 ,  이대우 ,  김상기 ,  박일용 ,  유병곤

IPC: G06F13/38

CPC classification number: G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

Abstract: PURPOSE: A data bus system for a microcontroller is provided to increase an operation speed and reduce power consumption by reducing load capacitance of a data bus forming the data bus system. CONSTITUTION: An external access bus(204) is used by the data out from a CPU(214) and the data entering an I/O(Input/Output)(212) or an internal memory(216) from the outside. An internal access bus(202) is used by the data entering the CPU, the data out from the I/O or the internal memory, and the data out from or entering a peripheral circuit(218). An internal memory test bus(206) is used by the data out through the I/O. The external and the internal access bus are connected with each other through a latch structure(208).

Abstract translation: 目的：提供微控制器的数据总线系统，通过减少形成数据总线系统的数据总线的负载电容来提高运行速度并降低功耗。 构成：外部访问总线（204）由CPU（214）输出的数据和从外部进入I / O（输入/输出）（212）或内部存储器（216）的数据）使用。 内部访问总线（202）由进入CPU的数据，来自I / O或内部存储器的数据以及从外围电路（218）输出或进入外围电路（218）的数据使用。 内部存储器测试总线（206）由数据通过I / O使用。 外部和内部访问总线通过锁存结构（208）彼此连接。

公开(公告)号：KR1020030042655A

公开(公告)日：2003-06-02

申请号：KR1020010073393

申请日：2001-11-23

Applicant: 한국전자통신연구원

Inventor： 양일석 ,  노태문 ,  김종대 ,  유병곤

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: PURPOSE: A ferroelectric memory cell array and a method for storing data by using the same are provided to form a memory cell array by using the ferroelectric memory cell array formed with a single transistor. CONSTITUTION: A ferroelectric memory cell array is formed with a plurality of memory cells(FM1-FMn,FMm-FMn+m), a plurality of word lines(WL1-WLn), a plurality of bit lines(BL1-BLm), a common source line(CSL), and a plurality of well lines(WELL1-WELLn,WELLm-WELLn+m). The memory cells are formed by stacking a ferroelectric layer, a gate, a source, and a drain on a substrate including a well. The word lines are connected with gates of the memory cells. The bit lines are connected with drains of the memory cells. The common source line is commonly connected with sources of the memory cells. The well lines are connected with wells of the memory cells. The well lines are separated electrically to each other.

Abstract translation: 目的：通过使用由单个晶体管形成的铁电存储单元阵列，提供铁电存储单元阵列和使用该存储单元阵列存储数据的方法以形成存储单元阵列。 构成：铁电存储单元阵列形成有多个存储单元（FM1-FMn，FMm-FMn + m），多个字线（WL1-WLn），多个位线（BL1-BLm）， 公共源线（CSL）和多条井线（WELL1-WELLn，WELLm-WELLn + m）。 存储单元通过在包括阱的衬底上层叠铁电体层，栅极，源极和漏极而形成。 字线与存储器单元的栅极连接。 位线与存储器单元的漏极连接。 公共源线通常与存储器单元的源相连。 井线与存储单元的孔连接。 井管线彼此电气分离。

公开(公告)号：KR1020020042228A

公开(公告)日：2002-06-05

申请号：KR1020000072033

申请日：2000-11-30

Applicant: 한국전자통신연구원

Inventor： 이원재 ,  유인규 ,  양일석 ,  유병곤 ,  조경익

IPC: H01L21/31

CPC classification number: H01L21/0228 ,  C23C16/409 ,  C23C16/45542 ,  C23C16/45544 ,  C23C16/50 ,  H01L21/02194 ,  H01L21/02197 ,  H01L21/02274 ,  H01L21/31691 ,  Y10S438/905

Abstract: PURPOSE: A formation method of a Sr-Ta-O thin film is provided to improve an electrical characteristic by forming a Sr-Ta-O thin film having a high dielectric constant and a low current leakage through an atomic vaporization using plasma. CONSTITUTION: A thermal treatment is performed at the temperature of 155 - 165 deg.C, after locating a substrate to a reactive chamber(119). Then, a source having a strontium tantalum ethoxide is injected to the reactive chamber(119) by a carrier gas. An evaporated source in the carrier gas is carried to the outer of the reactive chamber(119) by an Ar gas. A plasma is formed by injecting an oxygen into the reactive chamber(119). Then, the oxygen plasma is carried to the outer of the reactive chamber(119) using the Ar gas.

Abstract translation: 目的：提供Sr-Ta-O薄膜的形成方法，以通过使用等离子体通过原子蒸发形成具有高介电常数和低电流泄漏的Sr-Ta-O薄膜来改善电特性。 构成：在将基板定位到反应室（119）之后，在155-165℃的温度下进行热处理。 然后，通过载气将具有钽酸锶钽的源注入反应室（119）。 载气中的蒸发源通过Ar气输送到反应室（119）的外部。 通过将氧注射到反应室（119）中形成等离子体。 然后，使用Ar气体将氧等离子体运送到反应室（119）的外部。

公开(公告)号：KR1020010037449A

公开(公告)日：2001-05-07

申请号：KR1019990044998

申请日：1999-10-18

Applicant: 한국전자통신연구원

Inventor： 조채룡 ,  이원재 ,  유병곤 ,  유인규 ,  김보우

IPC: H01L29/786

Abstract: PURPOSE: A non-destructive read-out field effect transistor is provided to obtain enhanced stability by manufacturing an SBN thin film through an organic metal heat decomposition. CONSTITUTION: Ba 2-ethylhexanoate and Sr 2-ethylhexanoate are solved into xylene solvent and Nb-ethoxide is solved into 2-methoxyethanol to prepare a precursor solution. The precursor solution is deposited on a substrate to form an SBN thin film through spin-coating at 3000 rpm. The spin coated thin film is first dried at 150 deg.C for 5 minutes, and second dried at 450 deg.C for 5 minutes. The second drying is repeated to obtain a desired thickness of the thin film. Annealing is performed for the final crystallization at 850 deg.C under an oxygen or air atmosphere for 30 minutes to 1 hour.

Abstract translation: 目的：提供一种非破坏性的读出场效应晶体管，通过有机金属热分解制造SBN薄膜来获得更高的稳定性。 构成：将2-乙基己酸钡和Sr 2-乙基己酸酯溶解在二甲苯溶剂中，并将铌酸乙酯溶解在2-甲氧基乙醇中以制备前体溶液。 将前体溶液沉积在基底上以通过以3000rpm旋涂形成SBN薄膜。 旋涂的薄膜首先在150℃下干燥5分钟，然后在450℃下干燥5分钟。 重复第二次干燥以获得期望的薄膜厚度。 在氧气或空气气氛下，在850℃下进行退火30分钟至1小时。

公开(公告)号：KR1020010002725A

公开(公告)日：2001-01-15

申请号：KR1019990022661

申请日：1999-06-17

Applicant: 한국전자통신연구원

Inventor： 김시호 ,  유병곤 ,  김보우 ,  이원재

IPC: G11C16/00

Abstract: PURPOSE: A nonvolatile ferroelectric memory device and method for driving the device is provided to independently select only one cell when programming an information of the first state and the second state, thereby preventing a drain disturb at a nonselected cell. CONSTITUTION: A nonvolatile ferroelectric memory device includes a large number of ferroelectric transistor cells, a large number of word lines(W/L), a large number of source lines(S/L), a large number of bit lines(B/L), and a large number of well lines. The large number of ferroelectric transistor cells are arranged in a matrix in the direction of a row and a column. The large number of word lines are commonly connected to each gate electrode of the ferroelectric transistors in each row direction. The large number of source lines are commonly connected to one side junction of the ferroelectric transistor in each column direction. The large number of bit lines are commonly connected to other side of the ferroelectric transistors in each column direction. The large number of well lines are commonly connected to the well of the ferroelectric transistors in each column direction.

Abstract translation: 目的：提供用于驱动该器件的非易失性铁电存储器件和方法，用于在编程第一状态和第二状态的信息时独立地仅选择一个单元，从而防止非选定单元的漏极干扰。 构成：非易失性铁电存储器件包括大量的铁电晶体管单元，大量字线（W / L），大量源极线（S / L），大量位线（B / L ），还有大量井线。 大量的铁电晶体管单元沿行和列的方向排列成矩阵。 大量的字线通常连接到每个行方向上的铁电晶体管的每个栅电极。 大量的源极线通常连接到铁电晶体管的每个列方向的一侧结。 大量的位线在每个列方向上通常连接到铁电晶体管的另一侧。 大量的阱线在每个列方向上通常连接到铁电晶体管的阱。