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    LAMINATED HIGH-FREQUENCY MODULE
    131.
    发明申请
    LAMINATED HIGH-FREQUENCY MODULE 审中-公开
    层压高频模块

    公开(公告)号：US20110284281A1

    公开(公告)日：2011-11-24

    申请号：US13109030

    申请日：2011-05-17

    Applicant: Takahiro AKIYAMA

    Inventor： Takahiro AKIYAMA

    IPC: H05K1/11

    CPC classification number: H05K1/0218 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/0298 ,  H05K3/4611 ,  H05K2201/09327 ,  H05K2201/09336 ,  H05K2201/09618 ,  H05K2201/09972

    Abstract: In a laminated high-frequency module, a laminate includes a plurality of dielectric layers. In a lower layer region including some of the plurality of dielectric layers, a digital circuit is provided. In an interlayer region including some of the plurality of dielectric layers, a digital circuit and an analog circuit are arranged so that they do not overlap in plan view of the laminate. In an upper layer region including some of the plurality of dielectric layers, a digital circuit is provided. Digital ICs are mounted on the surface of the uppermost dielectric layer in the upper layer region. An inner-layer ground electrode is provided on substantially an entire boundary surface between the lower layer region and the interlayer region and on substantially an entire boundary surface between the interlayer region and the upper layer region. In the interlayer region, a digital line and an inner-layer ground electrode are alternately arranged in the lamination direction.

    Abstract translation: 在层压高频模块中，层叠体包括多个电介质层。 在包括多个电介质层中的一些的下层区域中，提供数字电路。 在包括多个电介质层中的一些的层间区域中，布置数字电路和模拟电路，使得它们在叠层的平面图中不重叠。 在包括多个电介质层中的一些的上层区域中，提供数字电路。 数字IC被安装在上层区域中最上层的电介质层的表面上。 内层接地电极设置在下层区域和层间区域之间的基本整个边界表面上以及在层间区域和上层区域之间的大致整个边界表面上。 在层间区域中，数字线和内层接地电极在层叠方向上交替布置。

    MULTILAYER FLEXIBLE PRINTED WIRING BOARD AND ELECTRONIC APPARATUS
    132.
    发明申请
    MULTILAYER FLEXIBLE PRINTED WIRING BOARD AND ELECTRONIC APPARATUS 审中-公开
    多层柔性印刷线路板和电子设备

    公开(公告)号：US20110139492A1

    公开(公告)日：2011-06-16

    申请号：US13033828

    申请日：2011-02-24

    Applicant: Mitsuhiko Sugane

    Inventor： Mitsuhiko Sugane

    IPC: H05K1/00

    CPC classification number: H05K1/0218 ,  H05K1/0366 ,  H05K1/0393 ,  H05K1/148 ,  H05K3/3447 ,  H05K3/363 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4635 ,  H05K2201/0715 ,  H05K2201/0723 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/096 ,  H05K2201/10303

    Abstract: A multilayer flexible printed circuit board includes a core material made of an insulating material having bendability. A solid layer is provided on one surface of the core material. The solid layer is made of an electrically conductive material to form a ground plane. A wiring layer is provided on the other surface of the core material. The wiring layer is made of an electrically conductive material having a controlled impedance. The core material, the solid layer and the wiring layer together form one set of lamination. A plurality of sets of the lamination are laminated via an insulation layer.

    Abstract translation: 多层柔性印刷电路板包括由具有弯曲性的绝缘材料制成的芯材。 在芯材的一个表面上设置固体层。 固体层由导电材料制成以形成接地平面。 在芯材的另一个表面上设置布线层。 布线层由具有受控阻抗的导电材料制成。 核心材料，固体层和布线层一起形成一组层压。 通过绝缘层层叠多组层叠体。

    PRINTED CIRCUIT BOARD
    133.
    发明申请
    PRINTED CIRCUIT BOARD 审中-公开
    印刷电路板

    公开(公告)号：US20110139489A1

    公开(公告)日：2011-06-16

    申请号：US12772469

    申请日：2010-05-03

    Applicant: Hee-Soo Yoon ,  Dong-Hwan Lee ,  Kyoung-Ho Lee ,  Yoon-Dong Kim ,  Su-Bong Jang

    Inventor： Hee-Soo Yoon ,  Dong-Hwan Lee ,  Kyoung-Ho Lee ,  Yoon-Dong Kim ,  Su-Bong Jang

    IPC: H05K1/00

    CPC classification number: H05K1/0227 ,  H05K1/0262 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09663

    Abstract: A printed circuit board is disclosed. The printed circuit board in accordance with an embodiment of the present invention can include an insulation substrate, a first ground, which is formed on one surface of the insulation substrate and connected to a first power source, a second ground, which is formed on one surface of the insulation substrate and connected to a second power source, a separator, which separates the first ground from the second ground, a first signal line, which is stacked on at least one of the first ground and the second ground, and a second signal line, which is stacked on at least one of the first ground and the second ground and is adjacent to the first signal line. The separator can include a curved part, which is bent in between the first signal line and the second signal line.

    Abstract translation: 公开了印刷电路板。 根据本发明的实施例的印刷电路板可以包括绝缘基板，第一接地，其形成在绝缘基板的一个表面上并连接到第一电源，第二接地形成在第一接地 绝缘基板的表面并且连接到第二电源，将第一接地与第二接地分离的隔离件，堆叠在第一接地和第二接地中的至少一个上的第一信号线，以及第二接地 信号线，其堆叠在第一接地和第二接地中的至少一个上并且与第一信号线相邻。 分离器可以包括在第一信号线和第二信号线之间弯曲的弯曲部分。

    Process for Making a Multilayer Circuit Device Having Electrically Isolated Tightly Spaced Electrical Current Carrying Traces
    134.
    发明申请
    Process for Making a Multilayer Circuit Device Having Electrically Isolated Tightly Spaced Electrical Current Carrying Traces 有权
    制造具有电隔离的多层电路装置的方法紧密间隔的电流携带痕迹

    公开(公告)号：US20090158581A1

    公开(公告)日：2009-06-25

    申请号：US12263416

    申请日：2008-10-31

    Applicant: Vinh T. Nguyen ,  Claude A.S. Hamrick

    Inventor： Vinh T. Nguyen ,  Claude A.S. Hamrick

    IPC: H05K3/10 ,  H01S4/00

    CPC classification number: H05K3/1258 ,  H05K3/108 ,  H05K3/125 ,  H05K3/243 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K2201/098 ,  H05K2203/013 ,  H05K2203/0568 ,  Y10T29/49002 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A process for making a multilayer circuit device having electrically isolated tightly spaced electrical current carrying traces, comprising of providing an insulative substrate having a first side coated with a layer of conductive metal intended to form a ground plane; providing a plurality of seed layer traces of a predetermined width of approximately 25 microns or less separated from each other by a predetermined distance of approximately 25 microns or less on a second side of the insulative substrate, the narrowness of such separation being essentially limited only by characteristics of the photoresist material to be deposited and developed therebetween and to withstand subsequent processing; developing ribs or barriers of photoresist forming vertical walls rising above the spaces separating the seed layer traces and defining valleys or channels thereover; depositing a desired thickness of conductive material over the seed layer traces and in the valleys or channels between the vertical walls; stripping away the resist ribs or barriers to leave conductive traces to be variously used as ground lines, signal lines and power lines; repeating the previous steps to develop a plurality of circuit boards; stacking the several circuit boards and joining them together with layers of insulative material; identifying particular ones of the traces as signal lines and other traces as power lines and/or ground lines; interconnecting at least some of the ground lines on one board to ground lines and/or ground planes on other boards by conductors extending through vias; interconnecting signal lines to signal input and output terminals; and perhaps to signal lines on other boards through vias; and interconnecting power lines to power input and output terminals, and perhaps to power lines on other boards through vias.

    Abstract translation: 一种用于制造具有电隔离的紧密间隔的电流载体轨迹的多层电路器件的方法，包括提供一个绝缘衬底，该绝缘衬底具有涂覆有用于形成接地平面的导电金属层的第一侧; 提供大约25微米或更小的预定宽度的多个种子层迹线，其在绝缘衬底的第二面上彼此隔开约25微米或更小的预定距离，这种分离的狭窄本质上仅受限于 要在其间沉积和显影的光致抗蚀剂材料的特性，并承受随后的加工; 显影光刻胶的肋或障碍物形成垂直壁，上面分开种子层迹线并在其上限定谷或沟道的空间上方; 在所述种子层迹线和所述垂直壁之间的谷或通道中沉积所需厚度的导电材料; 剥离抗蚀肋或障碍物，使导电迹线不同地用作接地线，信号线和电源线; 重复以前的步骤来开发多个电路板; 堆叠几个电路板并将其与绝缘材料层连接在一起; 将特定的迹线识别为信号线和其它迹线作为电力线和/或接地线; 将一个板上的至少一些接地线与通过通孔延伸的导体将其它板上的接地线和/或接地平面互连; 互连信号线到信号输入和输出端子; 也许通过通孔在其他董事会上发出信号; 并将电源线互连到电源输入和输出端子，并且可能通过通孔将其他电路板上的电源线连接起来。

    MULTI-LAYER CIRCUIT SUBSTRATE MANUFACTURING METHOD AND MULTI-LAYER CIRCUIT SUBSTRATE
    135.
    发明申请
    MULTI-LAYER CIRCUIT SUBSTRATE MANUFACTURING METHOD AND MULTI-LAYER CIRCUIT SUBSTRATE 审中-公开
    多层电路基板制造方法及多层电路基板

    公开(公告)号：US20090032285A1

    公开(公告)日：2009-02-05

    申请号：US11814698

    申请日：2005-01-27

    Applicant: Yoji Ueda ,  Susumu Matsuoka ,  Rikiya Okimoto ,  Shozo Ochi ,  Satoru Tomekawa

    Inventor： Yoji Ueda ,  Susumu Matsuoka ,  Rikiya Okimoto ,  Shozo Ochi ,  Satoru Tomekawa

    IPC: H05K3/46 ,  H05K1/14 ,  H05K1/00

    CPC classification number: H05K1/024 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/0191 ,  H05K2201/0355 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/10378 ,  H05K2203/061 ,  H05K2203/1461 ,  Y10T428/24843

    Abstract: A method of manufacturing a multilayered circuit board includes the steps of: manufacturing a laminated body by laminating a prepreg of a predetermined thickness on at least one surface of a double-sided circuit board having a grounding link and a signal wiring patterned on both surfaces thereof; and applying heat and pressure to the laminated body and completing a layered structure in which the signal wiring is laid inside the prepreg at a boundary between the double-sided circuit board and the prepreg, wherein prepreg sheets of a predetermined thickness are used in a completed layered structure so that a thickness of a prepreg of the double-sided circuit board is smaller than a distance between a surface of the prepreg on a side not opposed to the double-sided circuit board and the signal wiring laid inside the prepreg.

    Abstract translation: 一种制造多层电路板的方法包括以下步骤：通过在具有接地链路的双面电路板和在其两个表面上图案化的信号布线的至少一个表面层压预定厚度的预浸料来制造层压体 ; 并且对层压体施加热和压力，并且完成在双面电路板和预浸料坯之间的边界处将信号布线放置在预浸料坯内部的层状结构，其中预定厚度的预浸料片材用于完成 使得双面电路板的预浸料坯的厚度小于与双面电路板不相对的一侧上的预浸料坯的表面与布置在预浸料坯内部的信号线之间的距离。

    Multi-layer circuit board having signal, ground and power layers
    136.
    再颁专利
    Multi-layer circuit board having signal, ground and power layers 有权
    具有信号，接地和电源层的多层电路板

    公开(公告)号：USRE40068E1

    公开(公告)日：2008-02-19

    申请号：US10888966

    申请日：2004-07-09

    Applicant: Yu-Chiang Cheng

    Inventor： Yu-Chiang Cheng

    IPC: H05K1/03

    CPC classification number: H05K1/024 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/4688 ,  H05K2201/0145 ,  H05K2201/0191 ,  H05K2201/09327

    Abstract: A multi-layer circuit board includes first, second, third, fourth, fifth, sixth and seventh insulating substrates; first, second, third, fourth and fifth signal wiring layers; first and second ground wiring layers; and a power wiring layer. Each of the first and seventh insulating substrates has a thickness ranging from 2.5 to 6.5 mil. Each of the second, fourth and sixth insulating substrates has a thickness ranging from 3 to 9 mil. Each of the third and fifth insulating substrates has a thickness ranging from 3 to 23 mil. The first signal wiring layer has a first resistance with respect to the first ground wiring layer. The second signal wiring layer has a second resistance with respect to the first ground wiring layer and the power wiring layer. The third signal wiring layer has a third resistance with respect to the first ground wiring layer and the power wiring layer. The fourth signal wiring layer has a fourth resistance with respect to the second ground wiring layer and the power wiring layer. The fifth signal wiring layer has a fifth resistance with respect to the second ground wiring layer. The first, second, third, fourth and fifth resistances are within the range of 49.5 to 60.5 ohms.

    Abstract translation: 多层电路板包括第一，第二，第三，第四，第五，第六和第七绝缘基板; 第一，第二，第三，第四和第五信号布线层; 第一和第二接地布线层; 和电力布线层。 第一和第七绝缘基板中的每一个具有2.5至6.5密耳的厚度。 第二，第四和第六绝缘基板中的每一个具有3至9密耳的厚度。 第三和第五绝缘基板中的每一个具有3至23密耳的厚度。 第一信号布线层相对于第一接地布线层具有第一电阻。 第二信号布线层相对于第一接地布线层和电源布线层具有第二电阻。 第三信号布线层相对于第一接地布线层和电源布线层具有第三电阻。 第四信号布线层相对于第二接地布线层和电源布线层具有第四电阻。 第五信号布线层相对于第二接地布线层具有第五电阻。 第一，第二，第三，第四和第五电阻在49.5至60.5欧姆的范围内。

    Techniques for distributing current in a backplane assembly and methods for making the same
    138.
    发明授权
    Techniques for distributing current in a backplane assembly and methods for making the same 有权
    在背板组件中分配电流的技术及其制造方法

    公开(公告)号：US07154761B1

    公开(公告)日：2006-12-26

    申请号：US10778418

    申请日：2004-02-13

    Applicant: Sergio Camerlo ,  Irfan Elahi

    Inventor： Sergio Camerlo ,  Irfan Elahi

    IPC: H01R12/16

    CPC classification number: H05K1/141 ,  H01R12/523 ,  H05K1/0263 ,  H05K3/222 ,  H05K3/3447 ,  H05K2201/044 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/10303

    Abstract: A backplane assembly includes a main backplane having a first power conductor, a backplane strip having a second power conductor, and connecting members disposed between the main backplane and the backplane strip. The connecting members hold the backplane strip in a fixed position relative to the main backplane and electrically connect the first power conductor and the second power conductor. In one arrangement, the connecting members include source standoffs which extend from a source area of the main backplane to the backplane strip, and target standoffs which extend from a target area of the main backplane to the backplane strip. The source and target standoffs and the second power conductor provide a current path which increases current carrying capacity from the source area to the target area above that provided by the first power conductor alone. Thus, the backplane assembly is well-provisioned for distributing high currents to circuit boards.

    Abstract translation: 背板组件包括具有第一电源导体的主背板，具有第二电源导体的底板条和设置在主背板和背板条之间的连接构件。 连接构件将背板条相对于主底板固定在固定位置，并电连接第一电力导体和第二电力导体。 在一种布置中，连接构件包括从主背板的源区域延伸到背板条的源支座以及从主底板的目标区域延伸到底板条的目标支架。 源和目标支座和第二电力导体提供电流路径，其增加从源区域到目标区域的电流承载能力，高于由第一电力导体单独提供的电流路径。 因此，背板组件设计良好，用于将高电流分​​配给电路板。

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