公开(公告)号：EP0575292A1

公开(公告)日：1993-12-22

申请号：EP93810414.8

申请日：1993-06-09

Applicant: DYCONEX PATENTE AG

Inventor： Schmidt, Walter, Dr. ,  Martinelli, Marco

IPC: H05K3/00 ,  H05K3/42

CPC classification number: H05K3/42 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/4084 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572

Abstract: Das Verfahren zur Herstellung von verfluchteten Durchführungen durch Substratmaterialien, bei denen die Projektion der Ein- und Ausmündungen sich nicht decken, wird einerseits durch versetztes Anlegen von Ätzfenstern auf beiden Seiten und durch entsprechend starkes Unterätzen dieser Fenster charakterisiert. Durch Anlegen von zueinander verschobenen Ätzfenstern auf beiden Seiten des Substrates und Durchätzen des Substrates durch die angelegten Fenster ergeben sich im Substrat "schräge" Durchführungen. Man kann, allein durch entsprechende Anlage der Fenster auch verzweigte Durchführungen mit mehr als einer Ausmündung herstellen.

Abstract translation: 其特征在于，通过基板材料生产不对齐的通孔的过程，其中入口和出口的突起不重合，首先，通过在两侧以偏移方式设置蚀刻窗口，其次， ，通过足够强的所述窗口的底切。 通过布置相对于彼此移位的蚀刻窗，在基板的两侧和被蚀刻的基板上，通过布置的窗口，“倾斜”通孔导致基板。 也可以通过以适当的方式布置窗户来产生具有多个出口的分支通孔。

公开(公告)号：EP0303485A3

公开(公告)日：1989-11-08

申请号：EP88307441.1

申请日：1988-08-11

Applicant: BICC Public Limited Company

Inventor： Lawrence, Howard

IPC: H05K3/32 ,  H05K1/00 ,  H05K3/40

CPC classification number: H05K3/4046 ,  H05K1/118 ,  H05K3/0064 ,  H05K3/306 ,  H05K3/326 ,  H05K3/4611 ,  H05K2201/091 ,  H05K2201/09609 ,  H05K2201/10303 ,  H05K2201/1059 ,  H05K2201/2009

Abstract: A circuit board in which the patterns of electrically conductive strips and/or pads can be of either standard or non-standard form and which can be designed and assembled by a user comprises a rigid electrically insulating board 1 having a multiplicity of holes 2 through the board arranged in a pattern of rows and columns and, secured to one major surface of the board, a separately formed flexible sheet 4 of electrically insulating material carrying on the surface of the sheet remote from the board a pattern of electrically conductive strips and/or pads 8 which overlies holes in the board. The strips and/or pads 8 are of such an electrically conductive material and of such a thickness that, when a pin C is urged through an electrically conductive strip or pad and the underlying flexible sheet 4 into an underlying hole 2 in the board, electrically conductive material pierced by the pin will effect an electrical contact with the pin passing through the material.

Abstract translation: 导电条和/或焊盘的图案可以是标准形式或非标准形式并且可由用户设计和组装的电路板包括刚性电绝缘板1，其具有多个孔2穿过 板被布置成行和列的图案，并且固定到板的一个主表面，分开形成的电绝缘材料的柔性片4，其在片材的远离板的表面上承载导电条的图案和/或 垫板8覆盖板上的孔。 条和/或焊盘8具有这样的导电材料，并且具有这样的厚度，使得当销C被推动穿过导电条或焊盘并且下面的柔性片4进入板中的下面的孔2时，电 由引脚刺穿的导电材料将影响与引脚穿过材料的电接触。

公开(公告)号：EP0249688A2

公开(公告)日：1987-12-23

申请号：EP87103898.0

申请日：1987-03-17

Applicant: International Business Machines Corporation

Inventor： Hitchcock, Robert Brewster ,  Kellerman, Eduardo ,  Koons, John Paul

IPC: H05K1/00

CPC classification number: H05K1/115 ,  H05K1/0289 ,  H05K2201/09236 ,  H05K2201/09609

Abstract: A printed circuit board (20) for electric circuits is formed of plural layers of electrical conductors (22, 24, 26) and includes through holes (36) and vias (38) arranged in a regular pattern along points of a grid laid out along othorgonal axes of a Cartesian coordinate system.
Conductors (32, 34) of a layer (22, 24) are grouped together as multiple-conductor channels (44, 46) which are routed among the through holes (36) and the vias (38) to make electrical connections among the electrical components. An additional via (48) can be entered in a central portion of a grid cell by rerouting conductors of channels in the cell through arcuate segments, thereby permitting connection between conductors of channels on different layers while preserving the original grid pattern of through holes and vias.

Abstract translation: 用于电路的印刷电路板（20）由多层电导体（22,24,26）形成，并且包括沿着布置在其上的格栅的沿着规则图案布置的通孔（36）和通孔（38） 笛卡尔坐标系的Othorgonal轴。 层（22,24）的导体（32,34）被分组在一起作为在通孔（36）和通孔（38）之间布线的多导体通道（44,46），以在电气 组件。 可以通过弧形段重新路由单元中的通道的导体，从而允许在不同层上的通道的导体之间连接，同时保持通孔和通孔的原始网格图案，可以在网格单元的中心部分中输入另外的通孔（48） 。

公开(公告)号：EP0166289A3

公开(公告)日：1987-08-19

申请号：EP85107130

申请日：1985-06-11

Applicant: International Business Machines Corporation

Inventor： Kraus, Charles John ,  Stoller, Herbert Ivan ,  Wu, Leon Li-Heng

IPC: H05K01/00 ,  H01L23/52

CPC classification number: H01L23/5383 ,  H01L2224/16225 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/4629 ,  H05K2201/09609

Abstract: The wiring nets on a module are divided into two groups of planes, i.e., an upper group (5) in which wiring is placed along "north-south" and "east-west" directions and a lower group (6) in which wiring is placed along diagonal directions. All vias (R-vias) for connecting to the wiring pass through the upper group of planes but only half of the vias (D-vias) pass through the lower group of planes. Thus the spacing between the vias of the lower group of planes is greater than the spacing between the upper vias, allowing more lines per wiring channel in the lower group of planes.

公开(公告)号：EP0137694A3

公开(公告)日：1986-05-14

申请号：EP84305874

申请日：1984-08-29

Applicant: BURROUGHS CORPORATION (A MICHIGAN CORPORATION)

Inventor： BARROW, MICHAEL

IPC: H01P3/08 ,  H05K1/00 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H05K3/30

CPC classification number: H01P3/081 ,  H01P3/088 ,  H05K1/0237 ,  H05K1/024 ,  H05K1/0289 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/0191 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09609

公开(公告)号：EP0154909A2

公开(公告)日：1985-09-18

申请号：EP85102330.9

申请日：1985-03-01

Applicant: HOECHST AKTIENGESELLSCHAFT

Inventor： Seibel, Markus, Dr. Dipl.-Chem.

IPC: H05K3/42

CPC classification number: B05D5/12 ,  H05K1/0287 ,  H05K1/05 ,  H05K3/0094 ,  H05K3/062 ,  H05K3/108 ,  H05K3/426 ,  H05K3/427 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2203/1394

Abstract: © Es wird ein Verfahren zur Herstellung von durchkontaktierten elektrischen Leiterplatten beschrieben, bei dem eine Platte aus Isolierstoffmaterial mit in rasterartigem Muster angeordneten Durchkontaktierungslöchern versehen wird, deren Wandungen mit einer Metallschicht überzogen werden und die auf mindestens einer Seite mit einer leitfähigen Metallschicht bedeckt wird. Die Metallschicht wird nach dem Metallisieren der Löcher bildmässig abgedeckt, und die nicht abgedeckten Bereiche der Metallschicht werden entweder durch Metallablagerung verstärkt oder durch Ätzen entfernt. Zugleich mit der Metallschicht wird ein Teil der Löcher in der Weise abgedeckt, dass im fertigen Produkt nur der gewünschte Anteil aller Löcher als Leitkontakt wirksam wird. Das Verfahren erlaubt die Fertigung von vorgebohrtem bzw. vorgelochtem und vormetallisiertem Basismaterial für gedruckte Schaltungen in Grosserie.

Abstract translation: 描述了一种用于制造通孔电镀印刷电路板的方法，其中绝缘材料的基板设置有以栅格图案布置的电镀通孔，并且其壁被涂覆有导电 金属层。 该板在其至少一侧覆盖有导电金属层。 在金属化孔之后，金属层被成像地覆盖，未被覆盖的金属层的区域通过金属沉积或通过蚀刻去除而增强。 与金属层一起，部分孔被覆盖，使得只有所有孔的所需部分用作最终产品中的导电连接。 本发明的方法允许大规模制造用于印刷电路的预钻孔或预先预先金属化的基底材料。

公开(公告)号：EP0148506A2

公开(公告)日：1985-07-17

申请号：EP84116410.6

申请日：1984-12-27

Applicant: HITACHI, LTD.

Inventor： Tanaka, Minoru ,  Hirota, Kazuo ,  Murata, Akira ,  Kobayashi, Fumiuki ,  Takenaka, Takaji

IPC: H01C13/02 ,  H01C1/142 ,  H01L25/16

CPC classification number: H01C13/02 ,  H01C1/142 ,  H05K1/116 ,  H05K1/167 ,  H05K3/388 ,  H05K3/42 ,  H05K2201/0317 ,  H05K2201/09609 ,  H05K2203/0361

Abstract: Resistors (4; 4a, 4b) are formed on one surface of a board (1; 1a, 1b, 1c) having through hole conductors (2; 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2h', 7aa) arranged like a lattice, an electrode (6) is further formed on the surface of these resistors, and the electrodes over the through hole conductors are coaxially removed, thereby forming substantially disk-like resistors (4a, 4b).

Abstract translation: 电阻器（4; 4a，4b）形成在具有通孔导体（2; 2a，2b，2c，2d，2e，2f，2g，2h，2i， 2h min，7aa），在这些电阻器的表面上进一步形成电极（6），同时去除通孔导体上的电极，从而形成大致圆盘状的电阻（4a，4b）。

公开(公告)号：EP3148050A1

公开(公告)日：2017-03-29

申请号：EP16190695.3

申请日：2016-09-26

Applicant: Electrochem Solutions, Inc.

Inventor： DECKER, Gregory G. ,  PETERSON, Brian R. ,  JANKINS, Eric

IPC: H02J50/12 ,  H02J50/80 ,  H05K1/02

CPC classification number: H04B1/40 ,  H02J7/0029 ,  H02J7/025 ,  H02J50/10 ,  H02J50/12 ,  H02J50/80 ,  H02J2007/0037 ,  H02J2007/004 ,  H02M7/155 ,  H04B5/0031 ,  H04B5/0037 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/115 ,  H05K2201/0707 ,  H05K2201/09609

Abstract: A system for harnessing and conditioning wirelessly transmitted electrical energy by near field magnetic induction configured with various magnetic field shielding embodiments is disclosed. The shielding embodiments are designed to minimize electromagnetic interference and induced electrical current. The system comprises an electrical energy capture circuit (14) and a RF communication circuit (16). The electrical energy capture circuit (14) conditions and modifies the wirelessly received electrical energy. The RF communication circuit (16) enables the system to wirelessly communicate with its sub-circuits and other energy capture systems. The system comprises a tunable band stop filter (62) that is electrically connected to the RF communication sub-circuit (58). In addition, the RF communication sub-circuit (58) is configured with opposing electrically conductive plates that isolate and shield the circuit from an oscillating magnetic field.

Abstract translation: 公开了一种利用由各种磁场屏蔽实施例构成的近场磁感应来利用和调节无线传输电能的系统。 屏蔽实施例被设计成使电磁干扰和感应电流最小化。 该系统包括电能捕获电路（14）和RF通信电路（16）。 电能捕获电路（14）调节和修改无线接收的电能。 RF通信电路（16）使得系统能够与其子电路和其他能量捕获系统无线通信。 该系统包括电连接到RF通信子电路（58）的可调带阻滤波器（62）。 此外，RF通信子电路（58）配置有相对的导电板，其隔离并屏蔽电路与振荡磁场。

公开(公告)号：EP3039748A1

公开(公告)日：2016-07-06

申请号：EP14839711.0

申请日：2014-08-07

Applicant: FCI Asia Pte. Ltd.

Inventor： BRUNGARD, Thomas ,  PERCHERKE, Michael ,  KOLIVOSKI, Christopher J. ,  GIESKI, Christopher S. ,  EPPLEY, Nazareth ,  COPPER, Charles ,  GOOSSENS, Thierry

IPC: H01R12/71 ,  H01R13/11

CPC classification number: H01R12/7088 ,  H01R12/585 ,  H01R13/113 ,  H01R13/41 ,  H05K1/116 ,  H05K3/306 ,  H05K2201/09609 ,  H05K2201/0979 ,  H05K2201/10189 ,  Y10T29/49147

Abstract: In accordance with one embodiment, an electrical connector can be mounted to a first printed circuit board to obtain a first current capacity, and the electrical connector can be mounted to a second printed circuit board to obtain a second current capacity that is lower than the first current capacity.

公开(公告)号：EP2827364A4

公开(公告)日：2015-11-18

申请号：EP13760607

申请日：2013-02-12

Applicant: FUJI ELECTRIC CO LTD

Inventor： NAKAMURA YOUKO ,  NASHIDA NORIHIRO

IPC: H01L23/12 ,  H01L23/28 ,  H01L23/29 ,  H01L23/31 ,  H01L23/36 ,  H01L23/373 ,  H01L25/07 ,  H01L25/18

CPC classification number: H05K1/0296 ,  H01L21/56 ,  H01L21/563 ,  H01L23/12 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/01 ,  H01L25/072 ,  H01L31/048 ,  H01L33/52 ,  H01L33/56 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/115 ,  H05K1/185 ,  H05K2201/09609 ,  H05K2201/09727 ,  H05K2201/098 ,  H01L2924/00

Abstract: The present invention provides a resin-sealed type semiconductor device capable of keeping the adhesive properties of sealing resin and improving the reliability and the like of the module. This resin-sealed type semiconductor device is a semiconductor device including: a conductive-patterned insulating substrate 1; conductive blocks 3a, 3b fixed to conductive patterns 2a, 2b of the conductive-patterned insulating substrate 1; a semiconductor chip 6 fixed to each conductive block; a printed circuit board 9 that has a conductive post 8 fixed to the semiconductor chip; and a resin 11 for sealing these constituents. The semiconductor device is configured such that the average volume of a conductive film per unit area of each conductive pattern around a section thereof, to which the corresponding conductive block is fixed, is reduced from the conductive block toward the outside.