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    Semiconductor device
    141.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20040201062A1

    公开(公告)日：2004-10-14

    申请号：US10653198

    申请日：2003-09-03

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Masakazu Hirose ,  Fukashi Morishita

    IPC: H01L027/01

    CPC classification number: H01L27/1203 ,  H01L21/84

    Abstract: In a potential interconnection layer, when viewed from a plane, a plurality of power supply potential regions and ground potential regions are alternately provided, with an interlayer insulation layer lying therebetween. A contact plug penetrating a second insulation layer is provided to electrically connect a source/drain (S/D) region on one side of a selected field effect transistor with a selected power supply potential region. Similarly, a contact plug penetrating the second insulation layer is provided to electrically connect a source/drain (S/D) region on the other side of another selected field effect transistor with a selected ground potential region. By employing this structure, a semiconductor device having a plurality of semiconductor circuits in which a power supply potential and a ground potential can be stabilized regardless of the cross-sectional structure of the semiconductor device is provided.

    Abstract translation: 在潜在的互连层中，当从平面观察时，交替地设置多个电源电位区域和接地电位区域，层间绝缘层位于其间。 提供穿透第二绝缘层的接触插塞以将选定的场效应晶体管的一侧上的源极/漏极（S / D）区域与选定的电源电位区域电连接。 类似地，穿过第二绝缘层的接触插塞被提供以将另一个选择的场效应晶体管的另一侧上的源极/漏极（S / D）区域与选择的接地电位区域电连接。 通过采用这种结构，提供了具有能够稳定电源电位和接地电位的多个半导体电路的半导体器件，而与半导体器件的横截面结构无关。

    Non-volatile semiconductor memory device attaining high data transfer rate
    143.
    发明申请
    Non-volatile semiconductor memory device attaining high data transfer rate 有权
    非易失性半导体存储器件达到高数据传输速率

    公开(公告)号：US20040196696A1

    公开(公告)日：2004-10-07

    申请号：US10665010

    申请日：2003-09-22

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Tadaaki Yamauchi

    IPC: G11C011/34

    CPC classification number: G11C16/28

    Abstract: A reference cell is connected to two reference bit lines. In data access, when one reference bit line is driven to a selected state in response to a reference column select signal which is a decode result of a column address, a potential of a selected reference bit line is transmitted to a reference data bus line. A potential difference between the reference data bus line and a data bus line is amplified by a sense amplifier, and read data is output from an external terminal. During the access period, a reference bit line in a non-selected state is precharged to a ground potential in response to a reset signal at H level. In the next data access, when the non-selected reference bit line is selected, successive data reading is attained without waiting for a time period for precharging a bit line.

    Abstract translation: 参考单元连接到两个参考位线。 在数据访问中，当响应于作为列地址的解码结果的参考列选择信号将一个参考位线驱动到选择状态时，所选择的参考位线的电位被发送到参考数据总线。 参考数据总线与数据总线之间的电位差由读出放大器放大，从外部端子输出读取数据。 在访问期间，响应于H电平的复位信号，未选择状态的参考位线被预充电到地电位。 在接下来的数据访问中，当选择未选择的参考位线时，连续读取数据，而不用等待预定位线的时间段。

    Nonvolatile memory device and semiconductor device
    144.
    发明申请
    Nonvolatile memory device and semiconductor device 有权
    非易失性存储器件和半导体器件

    公开(公告)号：US20040196695A1

    公开(公告)日：2004-10-07

    申请号：US10805365

    申请日：2004-03-22

    Applicant: Renesas Technology Corp.

    Inventor： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

    IPC: G11C011/34

    CPC classification number: G11C16/10 ,  G11C16/0433

    Abstract: Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 iA to flow a current in the memory cell.

    Abstract translation: 这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。 当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。 此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。 并且，在恒定电流源晶体管中流动约1IA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

    Substrate cleaning device and a method for manufacturing electronic devices
    146.
    发明申请
    Substrate cleaning device and a method for manufacturing electronic devices 审中-公开
    基板清洗装置及其制造方法

    公开(公告)号：US20040195207A1

    公开(公告)日：2004-10-07

    申请号：US10690565

    申请日：2003-10-23

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Hiroshi Tanaka

    IPC: G01L021/30 ,  G01R031/00

    CPC classification number: H01L21/67109

    Abstract: In a substrate cleaning device, a substrate is held and is opposite to a plurality of heating/cooling components that can operate at different temperatures, the substrate and the heating/cooling components being separated to each other with a gap, which is filled with cleaning liquid. Chuck pins of resin with a low heat conductivity are used to hold the substrate, and the substrate is positioned such that it is not in contact with any component other than the chuck pins. In this way, the amount of etching can be adjusted for each portion of the substrate by controlling the temperature distribution on the substrate, thereby providing improved evenness of a surface within the plane of the substrate after a cleaning process.

    Abstract translation: 在基板清洗装置中，基板被保持并且与可在不同温度下操作的多个加热/冷却部件相对，基板和加热/冷却部件被间隔开，间隙被填充清洁 液体。 使用导热率低的树脂的卡盘销来保持基板，并且将基板定位成使其不与卡盘销以外的任何部件接触。 以这种方式，可以通过控制基板上的温度分布来调整基板的每个部分的蚀刻量，从而在清洁处理之后提供改善的基板平面内的表面的均匀度。

    Production management method using delivery date prediction
    147.
    发明申请
    Production management method using delivery date prediction 审中-公开
    使用交货日期预测的生产管理方法

    公开(公告)号：US20040193291A1

    公开(公告)日：2004-09-30

    申请号：US10667672

    申请日：2003-09-23

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Akiko Sakai

    IPC: G05B013/02

    CPC classification number: G06Q10/06 ,  Y02P90/14

    Abstract: A production management method includes the steps of: pre-storing production information including delivery date information, manufacturing apparatus information and lot information; calculating a scheduled shipping date for each lot on the basis of the production information; reading a delivery date of the lot; calculating the number of delay days of the lot; outputting an alarm to the lot when the number of delay days is a positive number; and analyzing the main cause of the delay of the lot and generating an expedite instruction when the number of delay days is larger than 1.

    Abstract translation: 一种生产管理方法，包括以下步骤：预先存储包括发货日期信息，制造装置信息和批量信息的生产信息; 根据生产信息计算每批的定期出货日期; 阅读批次的交货日期; 计算批次的延迟天数; 当延迟天数为正数时，向批次输出报警; 并分析当延误日数大于1时批次延误的主要原因，并产生快速指令。

    Semiconductor device including interconnection and capacitor, and method of manufacturing the same
    148.
    发明申请
    Semiconductor device including interconnection and capacitor, and method of manufacturing the same 审中-公开
    包括互连和电容器的半导体器件及其制造方法

    公开(公告)号：US20040192008A1

    公开(公告)日：2004-09-30

    申请号：US10653214

    申请日：2003-09-03

    Applicant: RENESAS TECHNOLOGY CORP.

    Inventor： Takeshi Matsunuma

    IPC: H01L021/20

    CPC classification number: H01L21/76801 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/76877 ,  H01L28/91

    Abstract: A method of manufacturing a semiconductor device including an interconnection and a capacitor formed with a Cu layer in accordance with the present invention includes the steps of forming an interlayer insulation layer, forming an interconnection hole and a capacitor hole in the interlayer insulation layer, filling the interconnection hole with the Cu layer to form an interconnection layer, and partly filling the capacitor hole with the Cu layer to form one electrode of the capacitor. The step of filling the interconnection hole with the Cu layer to form the interconnection layer and the step of partly filling the capacitor hole with the Cu layer to form one electrode of the capacitor are performed in a single process step. Thus, manufacturing process of the semiconductor device can be simplified.

    Abstract translation: 根据本发明的制造包括互连的半导体器件和由Cu层形成的电容器的方法包括以下步骤：在层间绝缘层中形成层间绝缘层，形成互连孔和电容器孔，填充 与Cu层的互连孔形成互连层，并用Cu层部分地填充电容器孔以形成电容器的一个电极。 用Cu层填充互连孔以形成互连层的步骤以及用Cu层部分地填充电容器孔以形成电容器的一个电极的步骤在单个工艺步骤中进行。 因此，可以简化半导体器件的制造工艺。

    Nonvolatile semiconductor memory device and manufacturing method thereof
    149.
    发明申请
    Nonvolatile semiconductor memory device and manufacturing method thereof 有权

    公开(公告)号：US20040191993A1

    公开(公告)日：2004-09-30

    申请号：US10819270

    申请日：2004-04-07

    Applicant: Renesas Technology Corp.

    Inventor： Takashi Kobayashi

    IPC: H01L021/336 ,  H01L029/788 ,  H01L021/8222

    CPC classification number: H01L27/11526 ,  G11C16/0425 ,  G11C16/0491 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546

    Abstract: A nonvolatile semiconductor memory device having a memory cell comprising source/drain diffusion layer in p-well formed to a silicon substrate, a floating gate as a first gate, a control gate (word line) as a second gate, and a third gate, in which the floating gate and the p-well are isolated by a tunnel insulator film, the third gate and the p-well are isolated by a gate insulator film, the floating gate and the third gate are isolated by an insulator film, the floating gate and the word line (control gate) are isolated by a insulator film (ONO film), and the second gate film and the word line (control gate) are isolated by a silicon oxide film, respectively, wherein the thickness of the tunnel insulator film is made larger than the thickness of the gate insulator film. Accordingly, the reliability and access time of the device is improved.

    Nonvolatile semiconductor memory device
    150.
    发明申请
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US20040183122A1

    公开(公告)日：2004-09-23

    申请号：US10766188

    申请日：2004-01-29

    Applicant: Renesas Technology Corp.

    Inventor： Toshiyuki Mine ,  Takashi Hashimoto ,  Senichi Nishibe ,  Nozomu Matsuzaki ,  Hitoshi Kume ,  Jiro Yugami

    IPC: H01L029/788

    CPC classification number: H01L29/66833 ,  G11C16/0466 ,  H01L21/28282 ,  H01L29/792

    Abstract: A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.

    Abstract translation: 一种非易失性半导体存储器件，由具有栅极绝缘膜和选择栅电极的选择MOS晶体管构成，以及具有电容绝缘膜的存储MOS晶体管，该MOS晶体管具有下部势垒膜，电荷俘获膜和 上电势势垒膜，以及存储栅电极。 电荷捕获膜由氧氮化硅膜形成，并且省略上电势阻挡膜或将其厚度限制在1nm以下，以防止由氮氧化硅膜引起的Gm劣化，从而降低擦除栅极电压。 电荷捕获膜由形成在氧氮化硅膜上或下面的主电荷俘获膜和氮化硅膜形成，以形成仅对孔有效的势垒。 并且，采用热孔擦除方法来降低擦除电压。

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